Sabre32 Reference Datasheet

February 11, 2010

CONFIDENTIAL ADVANCE

INFORMATION Rev. 1.2

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11

Vista™

High Definition

Vista™

High Definition

De-emphasis

The de-emphasis feature is included for audio data that has utilized the 50/15uS pre-emphasis for noise

reduction. There are 3 de-emphasis filters, one for 32 kHz, 44.1 kHz and 48 kHz.

The de-emphasis filter can automatically be applied when an SPDIF stream sets the de-emphasis flag. It

will auto detect the sample rate (32k, 44.1k, 48k) in either consumer or professional formats and then

apply the correct de-emphasis filter. The automatic enabling of the de-emphasis filter can be disabled in

Register 17 <en_auto>.

OSF Bypass

The oversampling FIR filter can be bypassed, sourcing data directly into the IIR filter. ESS recommends

using 8*Fs as the input. For example, an external signal at 44.1kHz can be oversampled externally to

8*44.1kHz = 352.8kHz and then applied to the serial decoder in either I2S, LJ or RJ format. The

maximum sample rate that can be applied is 1.536MHz (8*192kHz).

SPDIF Data Select

An SPDIF source multiplexer allows for up to eight SPDIF sources to be connected to the data pins on

the SABRE

32 Reference. The SABRE32 Reference uses an internal programmable register to select the

appropriate data pin to decode.

SPDIF input can be automatically decoded when there is valid SPDIF data if Register 17

<spdif_autodetect> is enabled.

Programmable Filter

The FIR filter can be programmed with custom coefficients to achieve an arbitrary frequency response

that suits the needs of the product. The two stage interpolated filter exploits the symmetry of the

coefficients to achieve a very sharp frequency response while using only 64 coefficients for the stage one

filter and 14 coefficients for the stage two filter. Custom coefficients can be enabled via register 37

<prog_coeff_enabled> and can be programmed via the method explained in the FIR Programmable

Filters section.

The length of the stage 2 filter is configurable to either 27 or 28 coefficients via register 17 <fir_length>.

System Clock (XI / MCLK)

A system clock is required for proper operation of the digital filters and modulation circuitry. Maximum

clock frequency is 100MHz. The system clock must also satisfy:

Data Type

Valid MCLK Frequencies

DSD Data

100MHz > MCLK > 3*Fs , Fs = 2.8224MHz

Serial Normal Mode

100MHz > MCLK > 192*Fs

Serial OSF Bypass Mode

100MHz > MCLK > 24*Fs

SPDIF Data

100MHz > MCLK > 386*Fs

Data Clock

DATA_CLOCK must be 64*Fs for SERIAL, Fs for DSD modes, and is not required for SPDIF mode. This

pin should be pulled low if not used.

Built-in Digital Filters

There are numerous applications for a stereo DAC so for added flexibility; two digital filter settings are

possible, sharp roll-off and a slow roll-off for PCM mode. For DSD mode, there are 4 available filters with

cutoffs at 47kHz, 50kHz, 60kHz, and 70kHz.