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HEC4027BDF 数据表(PDF) 4 Page - NXP Semiconductors

部件名 HEC4027BDF
功能描述  Dual JK flip-flop
PDF  5 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

HEC4027BDF 数据表(HTML) 4 Page - NXP Semiconductors

  HEC4027BDF Datasheet HTML 1Page - NXP Semiconductors HEC4027BDF Datasheet HTML 2Page - NXP Semiconductors HEC4027BDF Datasheet HTML 3Page - NXP Semiconductors HEC4027BDF Datasheet HTML 4Page - NXP Semiconductors HEC4027BDF Datasheet HTML 5Page - NXP Semiconductors  
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January 1995
4
Philips Semiconductors
Product specification
Dual JK flip-flop
HEF4027B
flip-flops
CD → O
5
75
150 ns
48 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
35
70 ns
24 ns
+ (0,23 ns/pF) CL
15
25
50 ns
17 ns
+ (0,16 ns/pF) CL
Output transition times
5
60
120 ns
10 ns
+
(1,0 ns/pF) CL
HIGH to LOW
10
tTHL
30
60 ns
9 ns
+ (0,42 ns/pF) CL
15
20
40 ns
6 ns
+ (0,28 ns/pF) CL
5
60
120 ns
10 ns
+
(1,0 ns/pF) CL
LOW to HIGH
10
tTLH
30
60 ns
9 ns
+ (0,42 ns/pF) CL
15
20
40 ns
6 ns
+ (0,28 ns/pF) CL
Set-up time
5
50
25
ns
see also waveforms
Figs 4 and 5
J,K
→ CP
10
tsu
30
10
ns
15
20
5
ns
Hold time
5
25
0
ns
J,K
→ CP
10
thold
20
0
ns
15
15
5
ns
Minimum clock
5
80
40
ns
pulse width; LOW
10
tWCPL
30
15
ns
15
24
12
ns
Minimum SD,CD
5
tWSDH,
tWCDH
90
45
ns
pulse width; HIGH
10
40
20
ns
15
30
15
ns
Recovery time
5
tRSD,
tRCD
20
−15
ns
for SD,CD
10
15
−10
ns
15
10
−5ns
Maximum clock
5
4
8
MHz
see also waveforms
Fig.4
pulse frequency
10
fmax
12
25
MHz
J = K = HIGH
15
15
30
MHz
VDD
V
TYPICAL FORMULA FOR P (
µW)
Dynamic power
5
900 fi +∑ (foCL) × VDD2
where
dissipation per
10
4 500 fi +∑ (foCL) × VDD2
fi = input freq. (MHz)
package (P)
15
13 200 fi +∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (f
oCL) = sum of outputs
VDD = supply voltage (V)
VDD
V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA



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