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HEC4027BDF 数据表(PDF) 3 Page - NXP Semiconductors

部件名 HEC4027BDF
功能描述  Dual JK flip-flop
PDF  5 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

HEC4027BDF 数据表(HTML) 3 Page - NXP Semiconductors

  HEC4027BDF Datasheet HTML 1Page - NXP Semiconductors HEC4027BDF Datasheet HTML 2Page - NXP Semiconductors HEC4027BDF Datasheet HTML 3Page - NXP Semiconductors HEC4027BDF Datasheet HTML 4Page - NXP Semiconductors HEC4027BDF Datasheet HTML 5Page - NXP Semiconductors  
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January 1995
3
Philips Semiconductors
Product specification
Dual JK flip-flop
HEF4027B
flip-flops
AC CHARACTERISTICS
VSS = 0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN.
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
CP
→ O, O
5
105
210 ns
78 ns
+ (0,55 ns/pF) CL
HIGH to LOW
10
tPHL
40
80 ns
29 ns
+ (0,23 ns/pF) CL
15
30
60 ns
22 ns
+ (0,16 ns/pF) CL
5
85
170 ns
58 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
35
70 ns
27 ns
+ (0,23 ns/pF) CL
15
30
60 ns
22 ns
+ (0,16 ns/pF) CL
SD → O
5
70
140 ns
43 ns
+ (0,55 ns/pF) CL
LOW to HIGH
10
tPLH
30
60 ns
19 ns
+ (0,23 ns/pF) CL
15
25
50 ns
17 ns
+ (0,16 ns/pF) CL
CD → O
5
120
240 ns
93 ns
+ (0,55 ns/pF) CL
HIGH to LOW
10
tPHL
45
90 ns
33 ns
+ (0,23 ns/pF) CL
15
35
70 ns
27 ns
+ (0,16 ns/pF) CL
SD → O
5
140
280 ns
113 ns
+ (0,55 ns/pF) CL
HIGH to LOW
10
tPHL
55
110 ns
44 ns
+ (0,23 ns/pF) CL
15
40
80 ns
32 ns
+ (0,16 ns/pF) CL
Fig.3 Logic diagram (one flip-flop).



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