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SIMPLIFIED SCHEMATIC OF P0 TO P7

Data From

Shift Register

Data From

Shift Register

Write Configuration

Pulse

Write Pulse

Read Pulse

Write Polarity

Pulse

Data From

Shift Register

Output Port

Register

Configuration

Register

Input Port

Register

Polarity

Inversion

Register

Polarity

Register Data

Input Port

Register Data

GND

ESD Protection

Diode

P0 to P7

Output Port

Register Data

Q1

Q2

D

FF

Q

Q

D

FF

Q

Q

D

FF

Q

Q

D

FF

Q

Q

To INT

I/O Port

PCA9534

WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS

SCPS124B – SEPTEMBER 2006 – REVISED FEBRUARY 2007

A.

At power-on reset, all registers return to default values.

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input

If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In

applied to this I/O pin should not exceed the recommended levels for proper operation.

connected to a positive supply through a pull-up resistor when connected to the output stages of a device. Data

transfer may be initiated only when the bus is not busy.

the SDA input/output while the SCL input is high (see Figure 1). After the start condition, the device address

byte is sent, MSB first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA

input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device

must not be changed between the start and the stop conditions.

stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control

commands (start or stop) (see Figure 2).

A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the

master (see Figure 1).

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