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Reads

A2

0

1

S

0

0

A1 A0 0

A

A

Data from Register

Slave Address

Slave Address

R/W

ACK From

Slave

Command Byte

ACK From

Slave

S

A2

0

1

0

0

A1 A0

R/W

1 A

Data

A

ACK From

Master

Data

Data from Register

NACK From

Master

NA P

Last Byte

ACK From

Slave

SCL

SDA

INT

Start

Condition

R/W

Read From

Port

Data Into

Port

Stop

Condition

ACK From

Master

NACK From

Master

ACK From

Slave

Data From Port

Slave Address

Data From Port

1

9

8

7

6

5

4

3

2

A2

0

1

S

0

0

A1 A0 0

A

Data 1

Data 4

A

NA P

Data 2

Data 3

Data 4

Data 5

PCA9534

WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS

SCPS124B – SEPTEMBER 2006 – REVISED FEBRUARY 2007

The bus master first must send the PCA9534 address with the least-significant bit set to a logic 0 (see Figure 4

for device address). The command byte is sent after the address and determines which register is accessed.

After a restart, the device address is sent again but, this time, the least-significant bit is set to a logic 1. Data

from the register defined by the command byte then is sent by the PCA9534 (see Figure 8 and Figure 9). After a

restart, the value of the register defined by the command byte matches the register being accessed when the

restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no

limitation on the number of data bytes received in one read transmission, but when the final byte is received, the

bus master must not acknowledge the data.

Figure 8. Read From Register

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A.

This figure assumes that the command byte has previously been programmed with 00h.

B.

Transfer of data can be stopped at any moment by a stop condition.

C.

This figure eliminates the command byte transfer, a restart and slave address call between the initial slave address

call and the actual data transfer from the P Port. See Figure 8 for these details.

Figure 9. Read Input Port Register

9

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