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NVP6124

Data sheet

02.11.2015 (REV 0.2)

19/125

4-CH AHD2.0 RX and 9-CH Audio Codec

2.10. Output Mode

The NVP6124 output to the back-end devices whether transferring a channel by a port or 2/4-

channels multiplexed output by a port. It is that as much as possible multiplexed channels by a

port

’s output frequency same to sum of multiplexed video’s frequency. The NVP6124 supports

that output of 27/36/37.125/54/72/74.25/108/144/148.5MHz Data Rate.

2.10.1

Single Output Mode

Basically, a video channel output through a port. NVP6124 output 4-clocks that VCLK1,

VCLK2, VCLK3, VCLK4 and output 4-data that VDO1[7:0], VDO2[7:0], VDO3[7:0], VDO4[7].

There is timing as shown in Figure 2.12. For VCLK1, VCLK2, VCLK3 and VCLK4 phase

adjustment can be made against VDO1~VDO4 using "Clock Delay Control" Register.

- (VCLK_x_SEL, 0xCC~CF[6:4], Control of Output Clock)

- (VCLK_x_DLY_SEL, 0xCC~CF[3:0], Control of Phase in Output Clock)

- (CH_OUT_SELx, 0xC8, 0xC9, Control how many multiplexed channel in a port)

Muxing

data of CH1

data of mixed CH1,2

data of mixed CH1,2,3,4

CHx_OUT_SEL

VDOx

ch1~4

ch1

time

multiplexer

VDOx

CHx_OUT_SEL

VCLK0x

VPORTx_SEQx

Muxing

ch1~4

ch2

Muxing

ch1~4

ch3

Muxing

ch1~4

ch4

Channel 1 data @ 27MHz

/ 36MHz

/ 37.125MHz

/ 74.25MHz(AHD)

/ 148.5MHz(AFHD)

CH1-a

CH1-b

All Port

(VDO1~VDO4)

27/36/37.125/74.25/148.5MHz Clock

(VCLK1~VCLK4)

Figure 2.12. Block Diagram of Single-Channel Output

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