AM29DL400B datasheet(16/47 Pages) AMD

16 / 47 page

Am29DL400B

Hardware Data Protection

The command sequence requirement of unlock cy-

cles for programming or erasing provides data

protection against inadvertent writes (refer to Table

5 for command definitions). In addition, the follow-

ing hardware data protection measures prevent

accidental erasure or programming, which might

otherwise be caused by spurious system level signals

during VCC power-up and power-down transitions, or

from system noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not ac-

cept any write cycles. This protects data during VCC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to reading array data. Subse-

quent writes are ignored until VCC is greater than

VLKO. The system must provide the proper signals to

the control pins to prevent unintentional writes when

VCC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE#

= VIL, CE# = VIH or WE# = VIH. To initiate a write

cycle, CE# and WE# must be a logical zero while

OE# is a logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power

up, the device does not accept commands on the ris-

ing edge of WE#. The internal state machine is

automatically reset to reading array data on

power-up.

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device

operations. Table 5 defines the valid register com-

mand sequences. Writing incorrect address and

data values or writing them in the improper se-

quence resets the device to reading array data.

All addresses are latched on the falling edge of WE#

or CE#, whichever happens later. All data is latched

on the rising edge of WE# or CE#, whichever hap-

pens first. Refer to the appropriate timing diagrams

in the AC Characteristics section.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. Each bank is ready to read array data

after completing an Embedded Program or Embed-

ded Erase algorithm.

After the device accepts an Erase Suspend com-

mand, the corresponding bank enters the erase-

suspend-read mode, after which the system can

read data from any non-erase-suspended sector

within the same bank. After completing a program-

ming operation in the Erase Suspend mode, the

system may once again read array data with the

same exception. See the Erase Suspend/Erase Re-

sume Commands section for more information.

The system must issue the reset command to return

a bank to the read (or erase-suspend-read) mode if

DQ5 goes high during an active program or erase op-

eration, or if the bank is in the autoselect mode. See

the next section, Reset Command, for more

information.

See also Requirements for Reading Array Data in the

Device Bus Operations section for more information.

The “Read-Only Operations” table provides the read

parameters, and Figure 13 shows the timing

diagram.

Reset Command

Writing the reset command resets the banks to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the bank to which the

system was writing to reading array data. Once era-

sure begins, however, the device ignores reset

commands until the operation is complete.

The reset command may be written between the se-

quence cycles in a program command sequence

before programming begins. This resets the bank to

which the system was writing to the reading array

data. If the program command sequence is written

to a bank that is in the Erase Suspend mode, writing

the reset command returns that bank to the erase-

suspend-read mode. Once programming begins,

however, the device ignores reset commands until

the operation is complete.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to reading array data. If a

bank entered the autoselect mode while in the Erase

Suspend mode, writing the reset command returns

that bank to the erase-suspend-read mode.

If DQ5 goes high during a program or erase opera-

tion, writing the reset command returns the banks to

reading array data (or erase-suspend-read mode if

that bank was in Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and devices

codes, and determine whether or not a sector is pro-

tected. Table 5 shows the address and data

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