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AM29BL802C 数据表(PDF) 13 Page - Advanced Micro Devices |
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AM29BL802C 数据表(HTML) 13 Page - Advanced Micro Devices |
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13 / 46 page  November 3, 2006 22371C7 Am29BL802C 11 D A TA SH EET gram or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 17 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high imped- ance state. Table 2. Sector Address Table Sector A18 A17 A16 A15 A14 A13 A12 Sector Size Address Range SA0 0 0 0 0 0 0 X 8 Kwords 00000h–01FFFh SA1 0 0 0 0 0 1 0 4 Kwords 02000h–02FFFh SA2 0 0 0 0 0 1 1 4 Kwords 03000h–03FFFh SA3 0 0 0 01, 11 X X 48 Kwords 04000h–0FFFFh SA4 0 0 1 X X X X 64 Kwords 10000h–1FFFFh SA5 0 1 0 X X X X 64 Kwords 20000h–2FFFFh SA6 0 1 1 X X X X 64 Kwords 30000h–3FFFFh SA7 1 0 X X X X X 128 Kwords 40000h–5FFFFh SA8 1 1 X X X X X 128 Kwords 60000h–7FFFFh |
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