44

Am29PL320D

June 13, 2005

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25

programming typicals assume checkerboard pattern.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 13 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

DATA RETENTION

* For reference only. BSC is an ANSI standard for Basic Space Centering.

BGA PACKAGE CAPACITANCE

Notes:

1. Sampled, not 100% tested.

Parameter

Typ

(Note 1)

Max

(Note 2)

Unit

Comments

Sector Erase Time, 96 and 128 KByte

sector

260

s

Excludes 00h programming

prior to erasure (Note 4)

Sector Erase Time, 8 and 16 KByte sector

0.5

60

Chip Erase Time

33.5

s

Word Programming Time

14.3

300

µs

Excludes system level

overhead (Note 5)

Double Word Programming Time

18.3

360

µs

Chip Programming Time

(Note 3)

Word Mode

28

84

s

Double Word

Mode

18

54

s

Description

Min

Max

(including A9 and OE#)

–1.0 V

12.5 V

–1.0 V

–100 mA

+100 mA

Parameter

Test Conditions

Min

Unit

Minimum Pattern Data Retention Time

150

°C

10

Years

125

°C

20

Years

Parameter Symbol

Parameter Description

Test Setup

Typ

Max

Unit

Input Capacitance

4.2

5.0

pF

Output Capacitance

5.4

6.5

pF

Control Pin Capacitance

3.9

4.7

pF