AM29PL320DB70WPI datasheet(11/49 Pages) AMD

11 / 49 page

June 13, 2005

Am29PL320D

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register it-

self does not occupy any addressable memor y

location. The register is composed of latches that store

the commands, along with the address and data infor-

mation needed to execute the command. The contents

of the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function

of the device. Table 1 lists the device bus operations,

the inputs and control levels they require, and the re-

sulting output. The following subsections describe

each of these operations in further detail.

Table 1.

Am29PL320D Device Bus Operations

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out

Notes:

1. Addresses are A19–A0 in double word mode (WORD# = VIH), A19–A-1 in word mode (WORD# = VIL).

2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

Word/Double Word Configuration

The WORD# input controls whether the device data

I/Os DQ31–DQ0 operate in the word or double word

configuration. If the WORD# input is set at VIH, the de-

vice is in double word configuration; DQ31–DQ0 are

active and controlled by CE# and OE#.

If the WORD# input is set at logic ‘0’, the device is in

word configuration, and only data I/Os DQ15–DQ0 are

active and controlled by CE# and OE#. The data I/Os

DQ30–DQ16 are tri-stated, and the DQ31 input is

used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# inputs to VIL. CE# is the power

control and selects the device. OE# is the output control

and gates array data to the output inputs. WE# should

remain at VIH. The WORD# input determines whether

the device outputs array data in words or bytes.

The internal state machine is set for reading array data

upon device power-up. This ensures that no spurious

alteration of the memory content occurs during the

power transition. No command is necessary in this

mode to obtain array data. Standard microprocessor

read cycles that assert valid addresses on the device

address inputs produce valid data on the device data

outputs. The device remains enabled for read access

until the command register contents are altered.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to Figure 13 for the timing diagram. ICC1 in

the DC Characteristics table represents the active cur-

rent specification for reading array data.

Read Mode

Random Read (Non-Page Mode Read)

The device has two control functions which must be

satisfied in order to obtain data at the outputs. CE# is

the power control and should be used for device selec-

tion. OE# is the output control and should be used to

gate data to the output inputs if the device is selected.

Address access time (tACC) is equal to the delay from

stable addresses to valid output data. The chip enable

access time (tCE) is the delay from the stable ad-

dresses and stable CE# to valid data at the output

inputs. The output enable access time is the delay

from the falling edge of OE# to valid data at the output

inputs (assuming the addresses have been stable for

at least tACC–tOE time).

Operation

CE#

OE#

WE#

WP#

Addresses

(Note 1)

DQ7–

DQ0

DQ31–DQ8

WORD#

= VIH

WORD#

= VIL

Read

AIN

DOUT

DQ30–DQ16 = High-Z,

DQ31 = A-1

Write

AIN

DIN

Standby

VCC ±

0.3 V

High-Z

Output Disable

High-Z

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