L320DB12VC datasheet(13/57 Pages) AMD

13 / 57 page

December 14, 2005

Am29LV320D

DA TA SH EET

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins operate in the byte or word configuration. If the

BYTE# pin is set at logic ‘1’, the device is in word con-

figuration, DQ0–DQ15 are active and controlled by

CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are

active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to VIL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at VIH. The BYTE# pin determines

whether the device outputs array data in words or

bytes.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

data on the device data outputs. The device remains

enabled for read access until the command register

contents are altered.

See “Requirements for Reading Array Data” on

page 11 for more infor mation. Refer to the AC

Read-Only Operations table for timing specifications

and to Figure 14, on page 38 for the timing diagram.

CC1 in the DC Characteristics table represents the ac-

tive current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to VIL, and OE# to VIH.

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes or

words. Refer to “Word/Byte Configuration” on page 11

for more information.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are re-

quired to program a word or byte, instead of four. The

“Word/Byte Configuration” on page 11 section con-

tains details on programming data to the device using

both standard and Unlock Bypass command se-

quences.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 2 on page 13 through

Table 5 on page 15 indicate the address space that

each sector occupies. A “sector address” is the ad-

dress bits required to uniquely select a sector.

CC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The “AC

Characteristics” on page 38 section contains timing

specification tables and timing diagrams for write oper-

ations.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This is one of two functions

provided by the WP#/ACC pin. This function is prima-

rily intended to allow faster manufacturing throughput

at the factory.

If the system asserts VHH on this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

VHH from the WP#/ACC pin returns the device to nor-

mal operation. Note that the WP#/ACC pin must not be

at VHH for operations other than accelerated program-

ming, or device damage may result. In addition, the

WP#/ACC pin must not be left floating or unconnected;

inconsistent behavior of the device may result.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. Refer to the “Autoselect Mode” on page 16

and “Autoselect Command Sequence” on page 25

sections for more information.

CC6 and ICC7 in the DC Characteristics table represent

the current specifications for read-while-program and

read-while-erase, respectively.

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