IMX7DCEC datasheet(36/161 Pages) NXP

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Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

Table 23. PCIe PHY reference clock Transmit requirements

Description

Symbol

Interface

Speed

Min Typ Max Unit

Frequency of TBC

FTBC

20-bit

1.5 Gbps

—

MHz

3.0 Gbps

—

150

—

6.0 Gbps

—

300

—

40-bit

1.5 Gbps

—

37.5

—

3.0 Gbps

—

6.0 Gbps

—

150

—

8-bit

2.5 Gbps

—

250

—

16-bit

5.0 Gbps

—

Duty cycle of TBC

DCTBC

—

TXD[0:30] setup time to the rising edge of TBC

TSETUP.TX

20-bit

1.5 Gbps

2.0

—

3.0 Gbps

6.0 Gbps

1.0

—

40-bit

1.5 Gbps

2.0

—

3.0 Gbps

6.0 Gbps

8-bit

2.5 Gbps

1.0

—

16-bit

5.0 Gbps

TXD[0:30] hold time to the rising edge of TBC

THOLD.TX

20-bit

1.5 Gbps

2.0

—

3.0 Gbps

6.0 Gbps

1.0

—

40-bit

1.5 Gbps

2.0

—

3.0 Gbps

6.0 Gbps

8-bit

2.5 Gbps

1.0

—

16-bit

5.0 Gbps

Latency from the rising edge of TBC to the leading edge

of the corresponding first transmitted serial output bit

TXP/TXN

TLAT.TX

—

1.5 Gbps

—

bits

2.5 Gbps

—

100

—

3.0 Gbps

—

5.0 Gbps

—

200

—

6.0 Gbps

—

120

—

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