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NE567D 数据表(PDF) 9 Page - NXP Semiconductors |
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NE567D 数据表(HTML) 9 Page - NXP Semiconductors |
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9 / 13 page ![]() Philips Semiconductors Linear Products Product specification NE/SE567 Tone decoder/phase-locked loop April 15, 1992 411 C 2 + 130 f O m F C 3 + 260 f O m F In cases where turn-off time can be sacrificed to achieve fast turn-on, the optional sensitivity adjustment circuit can be used to move the quiescent C3 voltage lower (closer to the threshold voltage). However, sensitivity to beat frequencies, noise and extraneous signals will be increased. OPTIONAL CONTROLS (Figure 3) The 567 has been designed so that, for most applications, no external adjustments are required. Certain applications, however, will be greatly facilitated if full advantage is taken of the added control possibilities available through the use of additional external components. In the diagrams given, typical values are suggested where applicable. For best results the resistors used, except where noted, should have the same temperature coefficient. Ideally, silicon diodes would be low-resistivity types, such as forward-biased transistor base-emitter junctions. However, ordinary low-voltage diodes should be adequate for most applications. DETECTION BAND — % OF fO Figure 6. BW Reduction NOTE: 130 f O 10k ) R R t C 2 t 1300 f O 10k ) R R Adjust control for symmetry of detection band edges about fO. 250 200 150 100 50 0 0 2 4 6 8 10 12 14 16 0.5k 0.9k 1.4k 1.9k 2.5k 3.2k 4.0k 10k 20k 100k R OPTIONAL SILICON DIODES FOR TEMPERATURE COMPENSATION PIN 2 567 V+ C2 RA RB RC R + R A ) R B R C R B ) R C 50k SENSITIVITY ADJUSTMENT (Figure 3) When operated as a very narrow-band detector (less than 8 percent), both C2 and C3 are made quite large in order to improve noise and out-band signal rejection. This will inevitably slow the response time. If, however, the output stage is biased closer to the threshold level, the turn-on time can be improved. This is accomplished by drawing additional current to terminal 1. Under this condition, the 567 will also give an output for lower-level signals (10mV or lower). By adding current to terminal 1, the output stage is biased further away from the threshold voltage. This is most useful when, to obtain maximum operating speed, C2 and C3 are made very small. Normally, frequencies just outside the detection band could cause false outputs under this condition. By desensitizing the output stage, the out-band beat notes do not feed through to the output stage. Since the input level must Figure 7. Output Latching NOTE: CA prevents latch-up when power supply is turned on. V+ C3 RL V+ CA RA 10k 567 8 1 UNLATCH 20k Rf V+ 567 8 1 20k C3 RL Rf UNLATCH V+ |
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