5

FN6462.0

February 26, 2007

Three-State Upper Gate Falling Threshold

VCC = 12V

-

1.96

-

V

Shutdown Holdoff Time

-

245

-

ns

UGATE Rise Time

-

26

-

ns

LGATE Rise Time

-

18

-

ns

UGATE Fall Time (Note 4)

-

18

-

ns

LGATE Fall Time (Note 4)

-

12

-

ns

UGATE Turn-On Propagation Delay (Note 4)

-

10

-

ns

LGATE Turn-On Propagation Delay (Note 4)

-

10

-

ns

UGATE Turn-Off Propagation Delay (Note 4)

-

10

-

ns

LGATE Turn-Off Propagation Delay (Note 4)

-

10

-

ns

LG/UG Three-State Propagation Delay (Note 4)

-

10

-

ns

OUTPUT

Upper Drive Source Current (Note 4)

-

1.25

-

A

Upper Drive Source Impedance

1.4

2.0

3.0

Ω

Upper Drive Sink Current (Note 4)

-

2

-

A

Upper Drive Sink Impedance

150mA Sink Current

0.9

1.65

3.0

Ω

Lower Drive Source Current (Note 4)

-

2

-

A

Lower Drive Source Impedance

0.85

1.3

2.2

Ω

Lower Drive Sink Current (Note 4)

-

3

-

A

Lower Drive Sink Impedance

150mA Sink Current

0.60

0.94

1.35

Ω

NOTE:

4. Guaranteed by design. Not 100% tested in production.

Electrical Specifications

Recommended Operating Conditions, Unless Otherwise Noted. (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Functional Pin Description

PACKAGE PIN #

PIN

SYMBOL

FUNCTION

SOIC

DFN

1

1

UGATE

Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.

2

2

BOOT

Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the

PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap

Device section under DESCRIPTION for guidance in choosing the capacitor value.

-

3,8

N/C

No Connection.

3

4

PWM

The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see

the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the

controller.

4

5

GND

Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.

5

6

LGATE

Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.

6

7

VCC

Connect this pin to a +12V bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND.

7

9

PVCC

This pin supplies power to both upper and lower gate drives in PX3511B; only the lower gate drive in PX3511A.

Its operating range is +5V to 12V. Place a high quality low ESR ceramic capacitor from this pin to GND.

8

10

PHASE

Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides

a return path for the upper gate drive.

9

11

PAD

Connect this pad to the power ground plane (GND) via thermally enhanced connection.

PX3511A, PX3511B