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PX3511ADAG-R3 数据表(PDF) 8 Page - Intersil Corporation |
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PX3511ADAG-R3 数据表(HTML) 8 Page - Intersil Corporation |
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8 / 10 page  8 FN6462.0 February 26, 2007 driver current can be estimated with Equations 2 and 3, respectively, where the gate charge (QG1 and QG2) is defined at a particular gate to source voltage (VGS1and VGS2) in the corresponding MOSFET datasheet; IQ is the driver’s total quiescent current with no load at both drive outputs; NQ1 and NQ2 are number of upper and lower MOSFETs, respectively; UVCC and LVCC are the drive voltages for both upper and lower FETs, respectively. The IQ*VCC product is the quiescent power of the driver without capacitive load and is typically 116mW at 300kHz. The total gate drive power losses are dissipated among the resistive components along the transition path. The drive resistance dissipates a portion of the total gate drive power losses, the rest will be dissipated by the external gate resistors (RG1 and RG2) and the internal gate resistors (RGI1 and RGI2) of MOSFETs. Figures 3 and 4 show the typical upper and lower gate drives turn-on transition path. The power dissipation on the driver can be roughly estimated as: Layout Considerations For heat spreading, place copper underneath the IC whether it has an exposed pad or not. The copper area can be extended beyond the bottom area of the IC and/or connected to buried copper plane(s) with thermal vias. This combination of vias for vertical heat escape, extended copper plane, and buried planes for heat spreading allows the IC to achieve its full thermal potential. Place each channel power component as close to each other as possible to reduce PCB copper losses and PCB parasitics: shortest distance between DRAINs of upper FETs and SOURCEs of lower FETs; shortest distance between DRAINs of lower FETs and the power ground. Thus, smaller amplitudes of positive and negative ringing are on the switching edges of the PHASE node. However, some space in between the power components is required for good airflow. The traces from the drivers to the FETs should be kept short and wide to reduce the inductance of the traces and to promote clean drive signals. P Qg_TOT P Qg_Q1 P Qg_Q2 I Q VCC • ++ = (EQ. 2) P Qg_Q1 Q G1 UVCC2 • V GS1 --------------------------------------- F SW • N Q1 • = P Qg_Q2 Q G2 LVCC2 • V GS2 -------------------------------------- F SW • N Q2 • = I DR Q G1 UVCC N Q1 • • V GS1 ------------------------------------------------------ Q G2 LVCC N Q2 • • V GS2 ----------------------------------------------------- + ⎝⎠ ⎜⎟ ⎛⎞ F SW I Q + • = (EQ. 3) P DR P DR_UP P DR_LOW I Q VCC • ++ = (EQ. 4) P DR_UP R HI1 R HI1 R EXT1 + -------------------------------------- R LO1 R LO1 R EXT1 + ---------------------------------------- + ⎝⎠ ⎜⎟ ⎛⎞ PQg_Q1 2 --------------------- • = P DR_LOW R HI2 R HI2 R EXT2 + -------------------------------------- R LO2 R LO2 R EXT2 + ---------------------------------------- + ⎝⎠ ⎜⎟ ⎛⎞ PQg_Q2 2 --------------------- • = R EXT1 R G1 R GI1 N Q1 ------------- + = R EXT2 R G2 R GI2 N Q2 ------------- + = FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH Q1 D S G RGI1 RG1 BOOT RHI1 CDS CGS CGD RLO1 PHASE UVCC LVCC Q2 D S G RGI2 RG2 RHI2 CDS CGS CGD RLO2 PX3511A, PX3511B |
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