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Revision History

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

This data manual revision history highlights the technical changes made to the SPRS346 device-specific

data manual to make it an SPRS346B revision.

Scope: Applicable updates to the C642x device family, specifically relating to the TMS320C6421 device,

have been incorporated.

• Upon exit from the bootloader code, all C64x+ memories are configured as all RAM, Cache is disabled.

• For proper C6421 device operation, clock ratio requirements must be met for the following peripheral

electrical data/timings: McASP0 and EMAC (MII/RMII Operation).

• This is now a complete document. New sections and subsections have been added.

SEE

ADDITIONS/MODIFICATIONS/DELETIONS

Global

Updated/Changed "DSP Subsystem" to "DSP"

Global

General-Purpose Input/Output (GPIO) pins shall be referred to as GP[x]. Register bit fields and interrupt

acronyms may be different (e.g., GPIO01 interrupt)

Section 2.2.2

Section 2.2.2, C64x+ Memory Architecture:

Table 2-2, C64x+ Cache Registers:

Added device-specific information relating to L1P, L1D, and L2 memory regions/ports.

Added "... (corresponds to byte address ...)" to MAR0 through MAR255 register DESCRIPTIONs for

clarification

Section 6.4.2

Section 6.4.2, EDMA Peripheral Register Description(s):

Table 6-7, C6421 EDMA Registers:

Added 0x01C0 0608 "QSTAT2" "Queue 2 Status Register"

Added "Command" to the register name for all RDRATE registers

Deleted "Source" from all SABIDX register names

Updated/Changed "BIDX" to "B-Index" for all DFBIDX0 through DFBIDX3 register names

Section 6.10.2

Section 6.10.2, UART Electrical Data/Timing:

Updated parameter signal names to "UTXDx" and "URXDx"

Updated signal names in Figure 6-19, UARTx Transmit/Receive Timing

Section 6.12.2

Section 6.12.2, HPI Peripheral Register Description(s):

Table 6-34, HPI Control Registers:

Updated/Changed the COMMENTS description for the PWREMU_MGMT register.

Updated/Changed the COMMENTS description for the HPIC register.

Updated/Changed the COMMENTS description for the HPIA (HIPAW/HPIAR) registers.

Updated/Changed the associated HPIA footnote.

Section 6.14.1.2

Section 6.14.1.2, McASP0 Peripheral Register Description(s):

Table 6-50, McASP0 Data Registers:

Updated/Changed the McASP0 Data Registers "ACRONYM" name from "XRBUF0" to "RBUF/XBUF".

Section 6.15.3.2

Section 6.15.3.2, EMAC RMII Electrical Data/Timing:

Table 6-61, Timing Requirements for RMREFCLK - RMII Operation:

Added "Cycle time, RMREFCLK" parameter

Updated Figure 6-40, RMREFCLK Timing [RMII Operation]

Section 6.19.2

Section 6.19.2, VLYNQ Electrical Data/Timing:

Table 6-81, RTM RX Data Flop Hold/Setup Timing Constraints:

Added RX Data Flop rows 6 and 7.

Section 6.20.2

Section 6.20.2, GPIO Peripheral Input/Output Electrical Data/Timing:

Updated/Changed GPIO pin names to "GP[x] input" or "GP[x] output" for clarity

Revision History

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