TMS320C6421 datasheet(95/227 Pages) TI

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TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346B – JANUARY 2007 – REVISED APRIL 2007

Table 3-20. Host Block Muxed Pins Selection

MULTIPLEXED FUNCTIONS

SIGNAL NAME

HPI

EMAC(MII)/MDIO

VLYNQ

GPIO

FUNCTION

SELECT

FUNCTION

SELECT

FUNCTION

SELECT

FUNCTION

SELECT

HOSTBK = 000

VLYNQ_CLOCK/GP[57]

–

VLYNQ_CLOCK

GP[57]

HOSTBK = 001

HOSTBK = 100

HD0/VLYNQ_SCRUN/GP[58]

HD0

–

VLYNQ_SCRUN

GP[58]

HD1/VLYNQ_RXD0/GP[59]

HD1

–

VLYNQ_RXD0

GP[59]

HOSTBK = 010

HD2/VLYNQ_RXD1/GP[60]

HD2

–

VLYNQ_RXD1

GP[60]

HOSTBK = 011

HD3/VLYNQ_RXD2/GP[61]

HD3

–

VLYNQ_RXD2

GP[61]

HOSTBK = 000

HD4/VLYNQ_RXD3/GP[62]

HD4

–

VLYNQ_RXD3

GP[62]

HOSTBK = 100

HD5/VLYNQ_TXD0/GP[63]

HD5

–

VLYNQ_TXD0

GP[63]

HD6/VLYNQ_TXD1/GP[64]

HD6

–

VLYNQ_TXD1

GP[64]

HD7/VLYNQ_TXD2/GP[65]

HD7

–

VLYNQ_TXD2

GP[65]

HD8/VLYNQ_TXD3/GP[66]

HD8

–

VLYNQ_TXD3

GP[66]

HD9/MCOL/GP[67]

HD9

MCOL

–

GP[67]

HD10/MCRS/GP[68]

HD10

MCRS

–

GP[68]

HD11/MTXD3/GP[69]

HD11

MTXD3

–

GP[69]

HD12/MTXD2/GP[70]

HD12

MTXD2

–

GP[70]

HOSTBK = 001

HD13/MTXD1/GP[71]

HD13

MTXD1

–

GP[71]

HD14/MTXD0/GP[72]

HD14

MTXD0

–

GP[72]

HD15/MTXCLK/GP[73]

HD15

MTXCLK

–

GP[73]

HHWIL/MRXDV/GP[74]

HHWIL

MRXDV

–

GP[74]

HOSTBK = 011

HOSTBK = 000

HCNTL1/MTXEN/GP[75]

HCNTL1

MTXEN

–

GP[75]

HOSTBK = 100

HOSTBK = 010

HCNTL0/MRXER/GP[76]

HCNTL0

MRXER

–

GP[76]

HR/W/MRXCLK/GP[77]

HR/W

MRXCLK

–

GP[77]

HDS2/MRXD0/GP[78]

HDS2

MRXD0

–

GP[78]

HDS1/MRXD1/GP[79]

HDS1

MRXD1

–

GP[79]

HRDY/MRXD2/GP[80]

HRDY

MRXD2

–

GP[80]

HCS/MDCLK/GP[81]

HCS

MDCLK

–

GP[81]

HINT/MRXD3/GP[82]

HINT

MRXD3

–

GP[82]

HAS/MDIO/GP[83]

HAS

MDIO

–

GP[83]

There is only one EMAC peripheral on the C6421 device, even though the pins for MII mode and the pins

for RMII modes are brought out to different locations. The EMAC MII mode pins are in the Host Block,

while EMAC RMII mode pins are only in the EMIFA Block. The user is only allowed to select either the MII

pins or the RMII pins. The operation is undefined if the user attempts to select both MII pins and RMII

pins.

Table 3-21 provides a different view of the Host Block pin muxing, showing the Host Block function based

on PINMUX1 settings. The selection options are also shown pictorially in Figure 3-10.

If EMAC operation is desired, EMAC must be placed in reset before programming PINMUX1.HOSTBK to

select EMAC pins.

Table 3-21. Host Block Function Selection

PINMUX1

SETTING

BLOCK FUNCTION

RESULTING PIN FUNCTIONS

HOSTBK

GPIO (27)

000

GPIO: GP[83:57]

(Default)

HPI: HHWIL, HCNTL[1:0], HR/W, HDS2, HDS1, HRDY, HCS, HINT, HAS, HD[15:0]

001

HPI + GPIO (1)

GPIO: GP[57]

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