TS4975

Application Information

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Table 14.

I²C control byte states

4.1.3

Acknowledge

The number of data bytes transferred between the start and the stop conditions from the CPU

master to the TS4975 slave is not limited. Each byte of eight bits is followed by one

acknowledge bit.

The TS4975 which is addressed, generates an acknowledge after the reception of each byte

that has been clocked out.

4.2

Output configuration

When the device is switched to Mode 5,6,7 or 8, where one channel is in shutdown, it means

that corresponding output is in a high impedance state.

4.2.1

Single-ended configuration

When the device is woken-up or switched via I²C interface to SE configuration, output amplifiers

4.2.2

Phantom ground configuration

In a PHG configuration the internal buffers are connected to PHG1 and PHG2 pins and biased

voltage. Therefore, no output capacitors are needed. The advantage of the PHG configuration

is the need for fewer external components as compared with a SE configuration. However, note

that the device has higher power dissipation (see

Section 4.3: Power dissipation and efficiency

In this configuration, PHG1 and PHG2 pins must be shorted and the connection between these

pins should be as short as possible. For best crosstalk results, in this case, each speaker

should be connected with a separate PHG wire (2 speakers connected with 4 wires) as shown

in

common PHG wire for both speakers (i.e. 2 speakers connected with 3 wires), which would give

much poorer crosstalk results.

4.2.3

Shutdown

When the device goes to shutdown from SE or PHG mode, PHG1 and PHG2 outputs are in a

high impedance state and OUT1 and OUT2 outputs are shorted together and connected to

implemented to reach the best pop performance during chip wake-up.

D7

(MSB)

D6

D5

D4

D3

D2

D1

D0

1

1

1

1

x

X

X

X

Undefined State