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TS4975 数据表(PDF) 31 Page - STMicroelectronics |
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TS4975 数据表(HTML) 31 Page - STMicroelectronics |
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31 / 36 page ![]() TS4975 Application Information 31/36 4.8 Startup time When the TS4975 is controlled to switch from full standby (output mode 0) to another output mode, a delay is necessary to stabilize the DC bias.This length of this delay depends on the Cb and VCC values. A typical value can be calculated by following formula: This formula assumes that Cb voltage is equal to 0 V. If the Cb voltage is not equal 0 V, the startup time will be always lower. In Figure 63 you could easily establish typical startup time for given supply voltage and bypass capacitor Cb. Figure 63. Typical startup time versus bypass capacitance 4.9 Pop and click performance The TS4975 has internal pop and click reduction circuitry which eliminates the output transients, for example during switch-on or switch-off phases, during a switch from an output mode to another or during change in volume. The performance of this circuitry is closely linked to the values of the input capacitor Cin, the output capacitor Cout (for Single-Ended configuration) and the bias voltage bypass capacitor Cb. The value of Cin and Cout is determined by the lower cut-off frequency value requested. The value of Cb will affect the THD+N and PSRR values in lower frequencies. The TS4975 is optimized to have a low pop and click in the typical schematic configuration (see Figure 1 on page 3 and Figure 2 on page 4). During the device start-up period when the pop and click reduction is active, the value $Fxh (1111xxxx binary) can be read from the internal device registry. Once the device is fully operational and the pop and click is inactive, the last value of control register can be read. t wu C b V CC V CC 1.2 – ------------------------- × 50000 0.008 s () + × = 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 0 50 100 150 200 250 300 350 400 Vcc=2.5V Vcc=3.3V Bypass capacitor Cb ( µF) Vcc=5V |
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