PCF2116CUSLASH10 datasheet(7/64 Pages) PHILIPS

7 / 64 page

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

PIN FUNCTIONS

7.1

RS: register select (parallel control)

RS selects the register to be accessed for read and write

when the device is controlled by the parallel interface.

RS = logic 0 selects the instruction register for write and

the Busy Flag and Address Counter for read. RS = logic 1

selects the data register for both read and write. There is

an internal pull-up on pin RS.

7.2

R/W: read/write (parallel control)

R/W selects either the read (R/W = logic 1) or write

(R/W = logic 0) operation when control is by the parallel

interface. There is an internal pull-up on this pin.

7.3

E: data bus clock

The E pin is set HIGH to signal the start of a read or write

operation when the device is controlled by the parallel

interface. Data is clocked in or out of the chip on the

negative edge of the clock. Note that this pin must be tied

to logic 0 (VSS) when I2C-bus control is used.

7.4

DB0 to DB7: data bus

The bidirectional, 3-state data bus transfers data between

the system controller and the PCF2116. DB7 may be used

as the Busy Flag, signalling that internal operations are not

yet completed. In 4-bit operations the 4 higher order lines

DB4 to DB7 are used; DB0 to DB3 must be left open

circuit. There is an internal pull-up on each of the data

lines. Note that these pins must be left open circuit when

I2C-bus control is used.

7.5

C1 to C60: column driver outputs

These pins output the data for pairs of columns.

This arrangement permits optimized chip-on-glass (COG)

layout for 4-line by 12 characters.

7.6

R1 to R32: row driver outputs

These pins output the row select waveforms to the left and

right halves of the display.

7.7

VLCD: LCD power supply

Negative power supply for the liquid crystal display.

This may be generated on-chip or supplied externally.

7.8

V0: VLCD control input

The input level at this pin determines the generated VLCD

output voltage.

7.9

OSC: oscillator

When the on-chip oscillator is used this pin must be

connected to VDD. An external clock signal, if used, is input

at this pin.

7.10

SCL: serial clock line

Input for the I2C-bus clock signal.

7.11

SDA: serial data line

Input/output for the I2C-bus data line.

7.12

SA0: address pin

The hardware sub-address line is used to program the

device sub-address for 2 different PCF2116s on the same

I2C-bus.

7.13

T1: test pad

Must be connected to VSS. Not user accessible.

FUNCTIONAL DESCRIPTION (see Fig.1)

8.1

LCD supply voltage generator, PCF2114x and

PCF2116x

The on-chip voltage generator is controlled by bit G of the

‘Function set’ instruction and V0.

V0 is a high-impedance input and draws no current from

the system power supply. Its range is between VSS and

VDD − 1 V. When V0 is connected to VDD the generator is

switched off and an external voltage must be supplied to

pin VLCD. This may be more negative than VSS.

When G = logic 1 the generator produces a negative

voltage at pin VLCD, controlled by the input voltage at

pin V0. The LCD operating voltage is given by the

relationship:

VOP = 1.8VDD − V0

Where:

VOP =VDD − VLCD

VLCD =V0 − (0.8VDD)

When G = logic 0, the generated output voltage VLCD is

equal to V0 (between VSS and VDD). In this instance:

VOP =VDD − V0

When VLCD is generated on-chip the VLCD pin should be

decoupled to VDD with a suitable capacitor. VDD and V0

must be selected to limit the maximum value of VOP to 9 V.

Figure 3 shows the two generator control characteristics.

PCF2116CU/10 数据表(PDF) 7 Page - NXP Semiconductors

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