PCF8566P datasheet(13/40 Pages) PHILIPS

13 / 40 page

1998 May 04

Philips Semiconductors

Product speciﬁcation

Universal LCD driver for low multiplex

rates

PCF8566

6.5

Oscillator

The internal logic and the LCD drive signals of the

PCF8566 or PCF8576 are timed either by the built-in

oscillator or from an external clock.

The clock frequency (fCLK) determines the LCD frame

frequency and the maximum rate for data reception from

the I2C-bus. To allow I2C-bus transmissions at their

maximum data rate of 100 kHz, fCLK should be chosen to

be above 125 kHz.

A clock signal must always be supplied to the device;

removing the clock may freeze the LCD in a DC state.

6.6

Internal clock

When the internal oscillator is used, OSC (pin 6) should be

tied to VSS. In this case, the output from CLK (pin 4)

provides the clock signal for cascaded PCF8566s and

PCF8576s in the system.

6.7

External clock

The condition for external clock is made by tying OSC

(pin 6) to VDD; CLK (pin 4) then becomes the external

clock input.

6.8

Timing

The timing of the PCF8566 organizes the internal data flow

of the device. This includes the transfer of display data

from the display RAM to the display segment outputs.

In cascaded applications, the synchronization signal

SYNC maintains the correct timing relationship between

the PCF8566s in the system. The timing also generates

the LCD frame frequency which it derives as an integer

multiple of the clock frequency (Table 3). The frame

frequency is set by MODE SET commands when internal

clock is used, or by the frequency applied to pin 4 when

external clock is used.

Table 3

LCD frame frequencies

The ratio between the clock frequency and the LCD frame

frequency depends on the mode in which the device is

operating. In the power saving mode the reduction ratio is

six times smaller; this allows the clock frequency to be

reduced by a factor of six. The reduced clock frequency

results in a significant reduction in power dissipation.

PCF8566 MODE

fframe

NOMINAL

fframe (Hz)

Normal mode

fCLK/2880

Power saving mode

fCLK/480

The lower clock frequency has the disadvantage of

increasing the response time when large amounts of

display data are transmitted on the I2C-bus. When a

device is unable to ‘digest’ a display data byte before the

next one arrives, it holds the SCL line LOW until the first

display data byte is stored. This slows down the

transmission rate of the I2C-bus but no data loss occurs.

6.9

Display latch

The display latch holds the display data while the

corresponding multiplex signals are generated. There is a

one-to-one relationship between the data in the display

latch, the LCD segment outputs and one column of the

display RAM.

6.10

Shift register

The shift register serves to transfer display information

from the display RAM to the display latch while previous

data are displayed.

6.11

Segment outputs

The LCD drive section includes 24 segment outputs

S0 to S23 (pins 17 to 40) which should be connected

directly to the LCD. The segment output signals are

generated in accordance with the multiplexed backplane

signals and with the data resident in the display latch.

When less than 24 segment outputs are required the

unused segment outputs should be left open-circuit.

6.12

Backplane outputs

The LCD drive section includes four backplane outputs

BP0 to BP3 which should be connected directly to the

LCD. The backplane output signals are generated in

accordance with the selected LCD drive mode. If less than

four backplane outputs are required the unused outputs

can be left open. In the 1 : 3 multiplex drive mode BP3

carries the same signal as BP1, therefore these two

adjacent outputs can be tied together to give enhanced

drive capabilities. In the 1 : 2 multiplex drive mode

BP0 and BP2, BP1 and BP3 respectively carry the same

signals and may also be paired to increase the drive

capabilities. In the static drive mode the same signal is

carried by all four backplane outputs and they can be

connected in parallel for very high drive requirements.

6.13

Display RAM

The display RAM is a static 24

× 4-bit RAM which stores

LCD data. A logic 1 in the RAM bit-map indicates the ‘on’

state of the corresponding LCD segment; similarly, a

logic 0 indicates the ‘off’ state.

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