PCF8566P datasheet(22/40 Pages) PHILIPS

22 / 40 page

1998 May 04

Philips Semiconductors

Product speciﬁcation

Universal LCD driver for low multiplex

rates

PCF8566

Table 7

LCD bias conﬁguration

Table 8

Display status

Table 9

Power dissipation mode

Table 10 Load data pointer

Table 11 Device select

Table 12 Input bank selection

Table 13 Output bank selection

Table 14 Blinking frequency

LCD BIAS

BIT B

⁄3bias

⁄2bias

DISPLAY STATUS

BIT E

Disabled (blank)

Enabled

MODE

BIT LP

Normal mode

Power-saving mode

BITS

5-bit binary value of 0 to 23

BITS

3-bit binary value of 0 to 7

STATIC

1 : 2 MUX

BIT 1

RAM bit 0

RAM bits 0, 1

RAM bit 2

RAM bits 2, 3

STATIC

1 : 2 MUX

BIT 0

RAM bit 0

RAM bits 0, 1

RAM bit 2

RAM bits 2, 3

BLINK

FREQUENCY

BIT BF1

BIT BF0

Off

2Hz

1Hz

0.5 Hz

Table 15 Blink mode selection

7.9

Display controller

The display controller executes the commands identified

by the command decoder. It contains the status registers

of the PCF8566 and coordinates their effects.

The controller is also responsible for loading display data

into the display RAM as required by the filling order.

7.10

Cascaded operation

In large display configurations, up to 16 PCF8566s can be

distinguished on the same I2C-bus by using the 3-bit

hardware subaddress (A0, A1 and A2) and the

programmable I2C-bus slave address (SA0). It is also

possible to cascade up to 16 PCF8566s. When cascaded,

several PCF8566s are synchronized so that they can

share the backplane signals from one of the devices in the

cascade. Such an arrangement is cost-effective in large

LCD applications since the outputs of only one device

need to be through-plated to the backplane electrodes of

the display. The other PCF8566s of the cascade

contribute additional segment outputs but their backplane

outputs are left open-circuit (Fig.17).

The SYNC line is provided to maintain the correct

synchronization between all cascaded PCF8566s.

This synchronization is guaranteed after the power-on

reset. The only time that SYNC is likely to be needed is if

synchronization is accidentally lost (e.g. by noise in

adverse electrical environments; or by the definition of a

multiplex mode when PCF8566s with differing SA0 levels

are cascaded). SYNC is organized as an input/output pin;

the output section being realized as an open-drain driver

with an internal pull-up resistor. A PCF8566 asserts the

SYNC line at the onset of its last active backplane signal

and monitors the SYNC line at all other times.

Should synchronization in the cascade be lost, it will be

restored by the first PCF8566 to assert SYNC. The timing

relationships between the backplane waveforms and the

SYNC signal for the various drive modes of the PCF8576

are shown in Fig.18. The waveforms are identical with the

parent device PCF8576. Cascade ability between

PCF8566s and PCF8576s is possible, giving cost effective

LCD applications.

BLINK MODE

BIT A

Normal blinking

Alternation blinking

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