1999 Jan 06

5

Philips Semiconductors

Product specification

256

× 8-bit static low-voltage RAM with

PCF8570

8

between different ICs or modules. The two lines are a

serial data line (SDA) and a serial clock line (SCL). Both

lines must be connected to a positive supply via a pull-up

resistor. Data transfer may be initiated only when the bus

is not busy.

8.1

Bit transfer

One data bit is transferred during each clock pulse.

The data on the SDA line must remain stable during the

HIGH period of the clock pulse as changes in the data line

at this time will be interpreted as a control signal.

Fig.3 Bit transfer.

MBA607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

8.2

Start and stop conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the

clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is

defined as the stop condition (P).

Fig.4 Definition of start and stop conditions.

MBA608

SDA

SCL

P

STOP condition

SDA

SCL

S

START condition