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PCF8575 数据表(PDF) 8 Page - NXP Semiconductors |
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PCF8575 数据表(HTML) 8 Page - NXP Semiconductors |
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8 / 24 page ![]() 1999 Apr 07 8 Philips Semiconductors Product specification Remote 16-bit I/O expander for I2C-bus PCF8575 7 FUNCTIONAL DESCRIPTION 7.1 Quasi-bidirectional I/Os The PCF8575’s 16 ports (see Fig.7) are entirely independent and can be used either as input or output ports. Input data is transferred from the ports to the microcontroller in the READ mode (see Fig.10). Output data is transmitted to the ports in the WRITE mode (see Fig.9). This quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data direction. At power-on the I/Os are HIGH. In this mode only a current source (IOH) to VDD is active. An additional strong pull-up to VDD (IOHt) allows fast rising edges into heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before being used as inputs. After power-on as all the I/Os are set HIGH all of them can be used as input. Any change in setting of the I/Os as either inputs or outputs can be done with the write mode. Warning: If a HIGH is applied to an I/O which has been written earlier to LOW, a large current (IOL) will flow to VSS. (see Characteristics note 3). 7.2 Addressing Figures 8, 9 and 10 show the address and timing diagrams. Before any data is transmitted or received the master must send the address of the receiver via the SDA line. The first byte transmitted after the START condition carries the address of the slave device and the read/write bit. The address of the slave device must not be changed between the START and the STOP conditions. The PCF8575 acts as a slave receiver or a slave transmitter. Fig.7 Simplified schematic diagram of each I/O. dbook, full pagewidth MGL540 DQ CI CI S FF D IOH IOL IOHt Q S FF 100 µA to interrupt logic VSS VDD P00 to P07 P10 to 17 write pulse data from shift register power-on reset read pulse data to shift register Fig.8 Byte containing the slave address and the R/W bits. MGL541 handbook, halfpage S 0 1 0 0 A2 A1 A0 R/W A slave address |
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