Philips Semiconductors

Product specification

PCK2000

CK97 (66/100MHz) System Clock Generator

1998 Sep 29

4

BLOCK DIAGRAM

PWRDWN

LOGIC

PWRDWN

LOGIC

STOP

LOGIC

STOP

LOGIC

PLL1

PLL2

14.318

MHZ

OSC

PWRDWN

LOGIC

LOGIC

SW00236

X

X

X

X

X

X

X

X

X

X

X

X

X

X

REFCLK [0–2](14.318 MHz)

PWRDWN

PCISTOP

CPUSTOP

SEL0

SEL1

SEL100/66

XTAL_IN

XTAL_OUT

IOAPIC [0–1](14.318 MHz)

48MHz [0–1](48MHz)

CPUCLK [0–3] (100MHz/66MHz)

PCICLK_F (33MHz)

PCICLK [1–7](33MHz)

SELECT FUNCTIONS

SEL100/66

SEL1

SEL0

FUNCTION

NOTES

0

0

0

TRI-State

1

0

0

1

Reserved

0

1

0

Reserved

0

1

1

Active 66MHz

1

0

0

Test mode

1

1

0

1

Reserved

1

1

0

Reserved

1

1

1

Active 100MHz

NOTE:

1. Internal decode logic for all three select inputs implemented.

FUNCTION

OUTPUTS

DESCRIPTION

CPU

PCI, PCI_F

48MHz

REF

IOAPIC

NOTES

3-STATE

HI-Z

HI-Z

HI-Z

HI-Z

HI-Z

TEST MODE

TCLK/2

TCLK/6

TCLK/2

TCLK

TCLK

NOTE:

1. TCLK is a test clock driven in on the XTAL_IN input in Test Mode.