Philips Semiconductors

Product specification

PCK2000

CK97 (66/100MHz) System Clock Generator

1998 Sep 29

9

REF(0–2) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

NOTES

MIN

MAX

f

Frequency, Actual

Frequency generated

by Crystal

14.31818

MHz

Output rise edge rate

1

4

ns

Output fall edge rate

1

4

ns

Duty Cycle

45

55

%

Frequency stabilization from Power-up (cold start)

3

ms

48MHZ(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

NOTES

MIN

MAX

f

Frequency, Actual

Determined by PLL

divider ratio

48.008

MHz

Devation from 48MHz

(48.008 – 48)/48

+167

ppm

Output rise edge rate

1

4

ns

Output fall edge rate

1

4

ns

Duty Cycle

45

55

%

Frequency stabilization from Power-up (cold start)

3

ms

ALL CLOCK OUTPUTS

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

NOTES

MIN

MAX

Output enable time

1.0

8.0

ns

Output disable time

1.0

8.0

ns

NOTES:

1. See Figure 3 for measure points.

2. Period, jitter, offset, and skew are measured on the rising edge @ 1.25V for 2.5V clocks and @ 1.5V for 3.3V clocks.

3. The PCICLK is the CPUCLK divided by two at CPUCLK = 66.6MHz. PCICLK is the CPUCLK divided by three at CPUCLK = 100MHz.

4. The CPUCLK must always lead the PCICLK as shown in Figure 2.

stable and operating within specification.

8. Defined as once the clock is at its nominal operating frequency, the adjacent period changes cannot exceed the time specified.