PCK2002PDP datasheet(5/8 Pages) PHILIPS

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Philips Semiconductors

Product data

PCK2002P

140 MHz PCI-X clock buffer

2001 May 09

AC CHARACTERISTICS

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

Tamb = –40 to +85 °C

UNIT

NOTES

MIN

TYP6

MAX

CLK HIGH time

66 MHz

6.0

—

CLK LOW time

66 MHz

6.0

—

CLK HIGH time

140 MHz

2.9

—

CLK LOW time

140 MHz

3.0

—

Output rise slew rate

1.4

1.7

4.0

V/ns

Output fall slew rate

1.5

2.2

4.0

V/ns

TPLH

Buffer LH propagation delay

1.8

2.9

3.4

TPHL

Buffer HL propagation delay

1.8

2.8

3.4

TSKW

Bus CLK skew

—

200

TDDSKW

Device to device skew

—

500

NOTES:

1. CLK skew is only valid for equal loading of all outputs.

2. TH is measured at 0.5 VDD as shown in Figure 2.

3. TL is measured at 0.35 VDD as shown in Figure 2.

4. TR and TF are measured as a transition through the threshold region 0.2 VDD to 0.6 VDD and 0.6 VDD to 0.2 VDD.

5. Input edge rate for these tests must be faster than 1 V/ns.

6. All typical values are at VCC = 3.3 V and Tamb = 25 °C.

AC WAVEFORMS

VM = 50% VDD

CL = 25 pF

VOL and VOH are the typical output voltage drop that occur with the

output load.

BUF_IN

INPUT

tPLH

tPHL

BUF_OUT

SW00811

VDD

0.6 VDD

0.2 VDD

0.6 VDD

0.2 VDD

Figure 1. Load circuitry for switching times.

0.5 VDD

0.4 VDD

0.35 VDD

SW00812

Figure 2. Buffer Output clock

TEST CIRCUIT

PULSE

GENERATOR

D.U.T.

VDD

140

Ω

140

Ω

SW00813

VDD

Figure 3. Load circuitry for switching times

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