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READ A CONVERSION/READ CYCLE

SDA

SCL

1

0

0

1

0

1

0

D11 D10

D9 D8 D7 D6 D5 D4

0

D3 D2 D1

D0

0

0

0

0

1

START

TSC2007

ACK

MASTER

ACK

MASTER

NACK

STOPor

Repeated

START

AddressByte

DataByte1

DataByte2

TSC2007

SBAS405 – MARCH 2007

idling prevents digital clock noise from affecting the bit decisions being made by the TSC2007. The master

should wait for at least 10

µs before attempting to read data from the TSC2007 to realize this best performance.

However, the master does not need to wait for a completed conversion before beginning a read from the slave,

if full 12-bit performance is not necessary.

Data access begins with the master issuing a START condition followed by the address byte (see Table 1) with

R/W = 1.

When the eighth bit has been received and the address matches, the slave issues an acknowledge. The first

byte of serial data will follow (D11-D4, MSB first).

After the first byte has been sent by the slave, it releases the SDA line for the master to issue an acknowledge.

The slave responds with the second byte of serial data upon receiving the acknowledge from the master (D3-D0,

followed by four 0 bits). The second byte is followed by a NOT acknowledge bit (ACK = 1) from the master to

indicate that the last data byte has been received. If the master somehow acknowledges the second data byte,

read transmission.

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