TSC2007IPW datasheet(28/41 Pages) TI

28 / 41 page

www.ti.com

THROUGHPUT RATE AND I2C BUS TRAFFIC

TSC2007

SBAS405 – MARCH 2007

Although the internal A/D converter has a sample rate of up to 200kSPS, the throughput presented at the bus is

much lower. The rate is reduced because preprocessing manages the redundant work of filtering out noise. The

throughput is further limited by the I2C bus bandwidth. The effective throughput is approximately 20kSPS at 8-bit

resolution, or 10kSPS at 12-bit resolution. This preprocessing saves a large portion of the I2C bandwidth for the

system to use on other devices.

Each sample and conversion takes 19 CCLK cycles (12-bit), or 16 CCLK cycles (8-bit). For a typical internal

4MHz OSC clock, the frequency actually ranges from 3.66MHz to 3.82MHz. For VDD = 1.2V, the frequency

drops down to 3.19MHz, which gives a 3.19MHz/16 = 199kSPS raw A/D converter sample rate.

To send the conversion result across the I2C bus takes 49 bus clocks (SCL clock). Each write cycle takes 20 I2C

cycles (START, STOP, address byte, 2 ACKs, and command byte). Each read cycle takes 29 I2C cycles

(START, STOP, address byte, 3 ACKs, and data bytes 1 and 2). Seven sample-and-conversions take 19 x 7

internal clocks (12-bit), or 16 x 7 (8-bit) to convert. The MAV filter loop takes 19 internal clocks. For VDD = 1.2V,

the complete processed data cycle time calculations are shown in Table 5. Because the first acquisition cycle is

overlapped with the I/O cycle, four CCLKs should be deducted from the total CCLK cycles. For 12-bit mode, it

requires (19

× 7 + 19) – 4 = 148 CCLKs plus I/O. For 8-bit mode, it requires (16 × 7 + 19) – 4 = 127 CCLKs plus

I/O.

Table 5. Measurement Cycle Time Calculations

STANDARD MODE: 100kHz (Period = 10

µs)

8-Bit

× 10µs + 127 × 313ns = 439.8µs (2.27kSPS through the I2C bus)

12-Bit

× 10µs + 148 × 625ns = 582.5µs (1.72kSPS through the I2C bus)

FAST MODE: 400kHz (Period = 2.5

µs)

8-Bit

× 2.5µs + 127 × 313ns = 139.8µs (7.15kSPS through the I2C bus)

12-Bit

× 2.5µs + 148 × 625ns = 215µs (4.65kSPS through the I2C bus)

HIGH-SPEED MODE: 1.7MHz (Period = 588ns)

8-Bit

× 588ns + 127 × 313ns = 63.3µs (15.79kSPS through the I2C bus)

12-Bit

× 588ns + 148 × 625ns = 121.3µs (8.24kSPS through the I2C bus)

HIGH-SPEED MODE: 3.4MHz (Period = 294ns)

8-Bit

× 294ns + 127 × 313ns = 51.6µs (19.39kSPS through the I2C bus)

12-Bit

× 294ns + 148 × 625ns = 106.9µs (9.35kSPS through the I2C bus)

As an example, use VDD = 1.2V and 12-bit mode with the Fast-mode I

2C clock (f

SCL = 400kHz). The equivalent

TSC throughput is at least seven times faster than the effective throughput across the bus (4.65k x 7 =

32.55kSPS). The supply current to the TSC for this rate and configuration is 128

µA. To achieve an equivalent

sample throughput of 8.2kSPS using the device without preprocessing, the TSC2007 merely consumes

(8.2/32.55)

× 128µA = 32.24µA.

Submit Documentation Feedback

TSC2007IPW 数据表(PDF) 28 Page - Texas Instruments

TSC2007IPW 数据表(HTML) 28 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

数据表下载

链接网址

TSC2007IPW 数据表(PDF) 28 Page - Texas Instruments

TSC2007IPW 数据表(HTML) 28 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

数据表 下载

链接网址

数据表下载