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TCS3410 数据表(PDF) 63 Page - OSRAM GmbH |
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TCS3410 数据表(HTML) 63 Page - OSRAM GmbH |
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63 / 85 page  Page 62 Datasheet, Public Document Feedback [v3-00] 2022-Dec-10 TCS3410 − Register O ver view VSYNC_CONTROL Register Figure 82: VSYNC_CONTROL Note(s): 1. Return to the Register Map (0xF6). Addr: 0xF6 VSYNC_CONTROL Bit Field Reset Type Bit Description 7:2 Reserved 0 1 HOLD_VSYNC_PERIOD 0 R/W If set to “1” VSYNC_PERIOD[15:8] and VSYNC_ PERIOD[7:0] cannot be updated until VSYNC_ PERIOD[15:8] has been read. It will avoid that updates during I²C readings. 0SW_VSYNC_TRIGGER 0 R/W If VSYNC_MODE is set to “1”, this bit can be used to trigger a SW sync. In case the exact time is known between two consecutive I²C reading the offset of the oscillator frequency can be calculated from the result in VSYNC_TRIGGER |
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