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TSL27721 数据表(PDF) 39 Page - OSRAM GmbH |
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TSL27721 数据表(HTML) 39 Page - OSRAM GmbH |
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39 / 58 page ![]() Page 38 Datasheet, Public Document Feedback [v2-00] 2023-Mar-30 TSL2772 − Principles O f Operation Configuration Register (0x0D) The configuration register sets the proximity LED drive level, wait long time, and ALS gain level. Figure 39: Configuration Register Proximity Pulse Count Register (0x0E) The proximity pulse count register sets the number of proximity pulses that the LDR pin will generate during the Prox Accum state. Figure 40: Proximity Pulse Count Register 76 5 4 3 2 1 0 Reserved AGL WLONG PDL Field Bits Description Reserved 7:3 Reserved. Write as 0. AGL 2 ALS gain level. When asserted, the 1x and 8x ALS gain (AGAIN) modes are scaled by 0.16. Otherwise, AGAIN is scaled by 1. Do not use with AGAIN greater than 8x. WLONG 1 Wait Long. When asserted, the wait cycles are increased by a factor 12x from that programmed in the WTIME register. PDL 0 Proximity drive level. When asserted, the proximity LDR drive current is reduced by 9. 76 5 4 3 2 1 0 PPULSE Field Bits Description PPULSE 7:0 Proximity Pulse Count. Specifies the number of proximity pulses to be generated. |
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