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33742 数据表(PDF) 21 Page - Freescale Semiconductor, Inc |
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33742 数据表(HTML) 21 Page - Freescale Semiconductor, Inc |
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21 / 65 page ![]() Analog Integrated Circuit Device Data Freescale Semiconductor 21 33742 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS Figure 7. SPI Timing Diagram Figure 8. Propagation Loop Delay TXD to RXD Figure 9. Propagation Delay TXD to CAN Figure 10. Propagation Delay CAN to RXD DI 0 DO 0 Undefined Don’t Care DI 8 Don’t Care tLEAD tSISU tWSCLKH DO 8 CS SCLK MOSI MISO Note Incoming data at MOSI pin is sampled by the 33742 at SCLK falling edge. Outgoing data at MISO pin is set by the 33742 at SCLK rising edge (after tVALID delay time). tSIH tWSCLKL tLAG tVALID tSOEN tSODIS tPCLK TXD 0.8 V tLRD 0.8 V RXD tLDR 2.0 V 2.0 V TXD 0.8 V tTRD 0.9 V VDIFF 2.0 V 0.5 V tTDR VDIFF = VCANH - VCANL VDIFF 0.9 V tRRD 2.0 V tRDR 0.8 V RXD 0.5 V |
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