33742 datasheet(28/65 Pages) FREESCALE

28 / 65 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33742

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Figure 12. RST and WDOG Output Operation

WAKE-UP CAPABILITIES

Several wake-up capabilities are available to the SBC

when it is in Sleep or Stop mode. When a wake-up has

occurred, the wake-up event is stored in the Wake-Up

determine the wake-up source. The wake-up options are

selectable through SPI while the 33742 is in Normal or

Standby mode and prior to entering low power modes (Sleep

or Stop mode). When a wake-up occurs in Sleep mode, the

SBC reactivates VDD supply. It generates an interrupt if

wake-up occurs from Stop mode.

WAKE-UP FROM WAKE-UP INPUTS (L0:L3)

WITHOUT CYCLIC SENSE

The wake-up lines are used to determine the state of

external switches and if changes occurred to wake up the

MCU (in Sleep or Stop modes). Wake-up pins L0:L3 are able

to handle up to 40 VDC. The internalize” threshold is 3.0 V

typical and these inputs can be used as an input port

expander. The wake-up input states are read through SPI

(WUR register).

In order to select and activate direct wake-up from the

L0:L3 inputs, the WUR register must be configured with the

appropriate level sensitivity. Additionally, the Low Power

Control (LPC) Register must be configured with 0xx0 data

(bits LX2HS and HSAUTO are set to 0).

The sensitivity of the L0:L3 inputs is selected by the WUR

L0 and L1 level sensitivity are configured together, while L2

and L3 are configured together.

CYCLIC SENSE WAKE-UP (CYCLIC SENSE TIMER

AND WAKE-UP INPUTS L0:L3)

The 33742 can wake up upon state change of one of the

four wake-up input lines (L0:L3). The external pullup or pull-

down resistor of the switches associated with the wake-up

input lines can be biased from the HS VSUP switch. The HS

switch is activated in Sleep or Stop modes from an internal

timer. Cyclic Sense and Forced Wake-Up are exclusive

states. If Cyclic Sense is enabled, Forced Wake-Up cannot

be enabled.

In order to select and activate the cyclic sense wake-up

from the L0:L3 inputs, the WUR register must be configured

with the appropriate level sensitivity and the LPC register

must be configured with 1xx1 data (bit LX2HS set at 1 and bit

HSAUTO set at 1). The wake-up mode selection (direct or

cyclic sense) is valid for all four wake-up inputs.

FORCED WAKE-UP

The SBC can wake up automatically after a predetermined

time spent in Sleep or Stop mode. Cyclic Sense and Forced

Wake-up are exclusive. If Forced Wake-Up is enabled (FWU

bit set to 1 in the LPC register), Cyclic Sense cannot be

enabled.

CAN INTERFACE WAKE-UP

The SBC incorporates a high-speed 1.0 Mbps CAN

physical interface. It is compatible with ISO 11898-2

standard. The operation of the CAN physical interface is

controlled through the SPI. The CAN operating modes are

independent of the 33742 operational modes.

The SBC can wake up from a CAN message if the CAN

wake-up feature is enabled. Refer to the section titled LOGIC

COMMANDS AND REGISTERS beginning on page 42 for

details of the wake-up detection.

SPI WAKE-UP

The 33742 can be awakened by changes on the CS pin in

Sleep or Stop modes. Wake-up is detected as a LOW-to-

HIGH level transition on the CS pin. In the Stop mode, this

corresponds to a condition where an MCU and the SBC are

both in the Stop mode and when the application wake-up

event comes through the MCU.

33742 POWER-UP AND WAKE-UP FROM SLEEP

MODE

After device or system power-up, or after the SBC

awakens from Sleep mode, the 33742S enters into the Reset

mode prior to moving into Normal Request mode.

Figure 13, shows the device state diagram. Figure 14,

shows device operation after power-up.

RST

WDOG

VDD

SPI

SPI CS

Watchdog Time-out

TIM1 register addressed.

Watchdog

Period

WDOG

Clear

33742 数据表(PDF) 28 Page - Freescale Semiconductor, Inc

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