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Mira130

Functional Description

Datasheet

• PUBLIC

DS000715

• v6-00 • 2023-Aug-09

│ 31

8.5

On-Chip PLL

The input clock frequency (FEXTCLK) of the phase locked loop (PLL) module ranges from 6 MHz to

27 MHz, while the VCO output frequency (FVCO) ranges from 400 MHz to 1200 MHz. The system clock

frequency FSYSCLK is obtained by dividing FVCO.

Figure 35 shows the PLL block diagram implemented on Mira130.

Figure 35:

PLL Block Diagram

8.5.1

Default Configurations and Clock Speeds

By default we provide some configuration files with predefined resolutions, framerates mipi lanes and

clock speeds. Contact your ams OSRAM application engineer for more information.

A typical configuration file is named according to the following example:

●

AMS_Trig_Mira130_4lane_800Mbps_24Minput_120fps_1080x1280.ini

From the filename, one can deviate the mipi clock speed (800Mbps x 4 lanes) with 24M main clock.

Generally, 24M MCLK corresponds to a Systemclk of 108M, 27M MCLK corresponds to a Systemclk

of 121.5M.

To calculate the internal pixel clock (TPCLK), the formula below applies:

pixel clock [MHz]=mipiclk [Mbps] / bit width * lane num

Pre_Divider

Divider

PFD

LPF

VCO

EX TCLK

FREFCLK

Divider

FVCO

FSYSCLK

511820003 数据表(PDF) 32 Page - OSRAM GmbH

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