MPC8323CVRADDC datasheet(65/80 Pages) FREESCALE

部件名	MPC8323CVRADDC

功能描述	PowerQUICC??II Pro Integrated Communications Processor Family Hardware Specifications

PDF	80 Pages

Scroll/Zoom	100%

制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

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65 / 80 page

MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

Clocking

22.4

System PLL Configuration

The system PLL is controlled by the RCWL[SPMF] parameter. Table 58 shows the multiplication factor

encodings for the system PLL.

As described in Section 22, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset

configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the

primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 59

shows the expected frequency values for the CSB frequency for select csb_clk to CLKIN/PCI_SYNC_IN

ratios.

Table 58. System PLL Multiplication Factors

RCWL[SPMF]

System PLL

Multiplication Factor

0000

Reserved

0001

Reserved

0010

× 2

0011

× 3

0100

× 4

0101

× 5

0110

× 6

0111–1111

Reserved

MPC8323CVRADDC 数据表(PDF) 65 Page - Freescale Semiconductor, Inc