AD9910SLASHPCBZ datasheet(42/60 Pages) AD

42 / 60 page

AD9910

Rev. 0 | Page 42 of 60

Software control requires that the EXT_PWR_DWN pin be

forced to a Logic 0 state. In this case, setting the desired power-

down bits (via the serial I/O port) powers down the associated

functional block, whereas clearing the bits restores the function.

Alternatively, all four functions can be simultaneously powered

down via external hardware control through the EXT_PWR_DWN

pin. When this pin is forced to Logic 1, all four circuit blocks are

powered down regardless of the state of the power-down bits.

That is, the independent power-down bits in CFR1 are ignored

and overridden when EXT_PWR_DWN is Logic 1.

Based on the state of the external power-down control bit, the

EXT_PWR_DWN pin produces either a full power-down or a

fast recovery power-down. The fast recovery power-down mode

maintains power to the DAC bias circuitry and the PLL, VCO,

and input clock circuitry. Although the fast recovery power-

down does not conserve as much power as the full power-down,

it allows the device to awaken very quickly from the power-

down state.

AD9910/PCBZ 数据表(PDF) 42 Page - Analog Devices