ADA4000-1/ADA4000-2/ADA4000-4

Rev. 0 | Page 10 of 16

APPLICATIONS

OUTPUT PHASE REVERSAL AND INPUT NOISE

Phase reversal is a change of polarity in the transfer function of

the amplifier. This can occur when the voltage applied at the

input of the amplifier exceeds the maximum common-mode

voltage. Phase reversal happens when the part is configured in

the gain of 1.

Most JFET amplifiers invert the phase of the input signal if the

input exceeds the common-mode input. Phase reversal is a

temporary behavior of the ADA4000-x family. Each part

returns to normal operation by bringing back the common-

mode voltage. The cause of this effect is saturation of the input

stage, which leads to the forward-biasing of a drain-gate diode.

In noninverting applications, a simple fix for this is to insert a

series resistor between the input signal and the noninverting

terminal of the amplifier. The value of the resistor depends on

the application, because adding a resistor adds to the total input

noise of the amplifier. The total noise density of the circuit is

()

S

S

n

n

nTOTAL

kTR

R

i

e

e

4

2

2

+

+

=

where:

T is the ambient temperature in Kelvin (T = 273 + °C).

In general, it is good practice to limit the input current to less

than 5 mA to avoid driving a great deal of current into the

amplifier inputs.

CAPACITIVE LOAD DRIVE

The ADA4000-1/ADA4000-2/ADA4000-4 are stable at all gains

in both inverting and noninverting configurations. The parts

are capable of driving up to 1000 pF of capacitive loads without

oscillations in unity gain configurations.

However, as with most amplifiers, driving larger capacitive loads

in a unity gain configuration can cause excessive overshoot and

ringing. A simple solution to this problem is to use a snubber

network (see Figure 30).

ADA4000-1

V+

V–

+15V

–15V

500pF

10kΩ

0

SNUBBER NETWORK

400mV p-p

0

V1

3

2

1

U1

Figure 30. Snubber Network Configuration

The advantage of this compensation method is that the swing at

network, and the gain accuracy does not change. Depending on

change, and the optimum value can be determined empirically.

In Figure 31, the oscilloscope image shows the output of the

ADA4000-x family in response to a 400 mV pulse. The circuit is

configured in the unity gain configuration with 500 pF in

parallel with 10 kΩ of load capacitive.

TIME (1µs/DIV)

INPUT SIGNAL

OUTPUT SIGNAL

Figure 31. Capacitive Load Drive Without Snubber Network

When the snubber circuit is used, the overshoot is reduced from

30% to 6% with the same load capacitance. Ringing is virtually

TIME (1µs/DIV)

INPUT SIGNAL

OUTPUT SIGNAL

Figure 32. Capacitive Load with Snubber Network