DSP56366P datasheet(78/110 Pages) FREESCALE

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DSP56366 Technical Data, Rev. 3.1

3-52

Freescale Semiconductor

3.13.1

Programming the Serial Clock

The programmed serial clock cycle, TI2CCP, is specified by the value of the HDM[7:0] and HRS bits of the

HCKR (SHI clock control register).

The expression for TI2CCP is

where

HRS is the prescaler rate select bit. When HRS is cleared, the fixed divide-by-eight

prescaler is operational. When HRS is set, the prescaler is bypassed.

HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256

(HDM[7:0] = $00 to $FF) may be selected.

In I2C mode, the user may select a value for the programmed serial clock cycle from

The programmed serial clock cycle (TI2CCP), SCL rise time (TR), and the filters selected should be chosen

in order to achieve the desired SCL serial clock cycle (TSCL), as shown in Table 3-21.

EXAMPLE:

For DSP clock frequency of 120 MHz (i.e. TC = 8.33ns), operating in a standard mode I2C environment

(FSCL = 100 kHz (i.e. TSCL = 10μs), TR = 1000ns), with wide filters enabled:

Choosing HRS = 0 gives

Thus the HDM[7:0] value should be programmed to $41 (=65).

Table 3-21 SCL Serial Clock Cycle (TSCL) generated as Master

Filters bypassed

TI2CCP + 2.5 × TC + 45ns + TR

Narrow filters enabled

TI2CCP + 2.5 × TC + 135ns + TR

Wide filters enabled

TI2CCP + 2.5 × TC + 223ns + TR

2CCP

[

HDM 7:0

[]

(

)

71 HRS

–

() 1

()

×]

6TC if

HDM 7:0

[]

02 and HRS

4096 TC if

HDM 7:0

[]

FF and HRS

2CCP

μs 2.5 8.33ns

223ns 1000ns

–

8756ns

HDM 7:0

[]

8756ns 2

(

8.33ns

) 1

64.67

–

⁄

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