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56F8335 数据表(PDF) 83 Page - Freescale Semiconductor, Inc |
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56F8335 数据表(HTML) 83 Page - Freescale Semiconductor, Inc |
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83 / 160 page ![]() Register Descriptions 56F8335 Technical Data, Rev. 5 Freescale Semiconductor 83 Preliminary • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.6 Interrupt Priority Register 5 (IPR5) Figure 5-8 Interrupt Priority Register 5 (IPR5) 5.6.6.1 Quadrature Decoder 1 INDEX Pulse Interrupt Priority Level (DEC1_XIRQ IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.6.2 Quadrature Decoder 1 HOME Signal Transition or Watchdog Timer Interrupt Priority Level (DEC1_HIRQ IPL)—Bits 13–12 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.6.3 SCI 1 Receiver Full Interrupt Priority Level (SCI1_RCV IPL)— Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 Base + $5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read DEC1_XIRQ IPL DEC1_HIRQ IPL SCI1_RCV IPL SCI1_RERR IPL 0 0 SCI1_TIDL IPL SCI1_XMIT IPL SPI0_XMIT IPL Write RESET 0 0 000 0 0 0 0000000 0 |
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