56F8335 datasheet(92/160 Pages) FREESCALE

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56F8335 Technical Data, Rev. 5

Freescale Semiconductor

Preliminary

5.6.10.7 ADC A Conversion Complete Interrupt Priority Level

(ADCA_CC IPL)—Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 0

•

10 = IRQ is priority level 1

•

11 = IRQ is priority level 2

5.6.10.8 ADC B Conversion Complete Interrupt Priority Level

(ADCB_CC IPL)—Bits 1–0

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 0

•

10 = IRQ is priority level 1

•

11 = IRQ is priority level 2

5.6.11 Vector Base Address Register (VBA)

Figure 5-13 Vector Base Address Register (VBA)

5.6.11.1 Reserved—Bits 15–13

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.11.2 Interrupt Vector Base Address (VECTOR BASE ADDRESS)—

Bits 12–0

The contents of this register determine the location of the Vector Address Table. The value in this register

is used as the upper 13 bits of the interrupt Vector Address Bus (VAB[20:0]). The lower eight bits are

determined based upon the highest-priority interrupt. They are then appended onto VBA before presenting

the full interrupt address to the 56800E core; see Part 5.3.1 for details.

Base + $A

Read

VECTOR BASE ADDRESS

Write

RESET

00000

0000000

0000

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