56F8335 datasheet(104/160 Pages) FREESCALE

104 / 160 page

56F8335 Technical Data, Rev. 5

104

Freescale Semiconductor

Preliminary

6.5.1.4

Stop Disable (STOP_DISABLE)—Bits 3–2

•

00 = Stop mode will be entered when the 56800E core executes a STOP instruction

•

01 = The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can be

reprogrammed in the future

•

10 = The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can then only be

changed by resetting the device

•

11 = Same operation as 10

6.5.1.5

Wait Disable (WAIT_DISABLE)—Bits 1–0

•

00 = Wait mode will be entered when the 56800E core executes a WAIT instruction

•

01 = The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can be

reprogrammed in the future

•

10 = The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can then only

be changed by resetting the device

•

11 = Same operation as 10

6.5.2

SIM Reset Status Register (SIM_RSTSTS)

Bits in this register are set upon any system reset and are initialized only by a Power-On Reset (POR). A

reset (other than POR) will only set bits in the register; bits are not cleared. Only software should clear this

Figure 6-4 SIM Reset Status Register (SIM_RSTSTS)

6.5.2.1

Reserved—Bits 15–6

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.2.2

Software Reset (SWR)—Bit 5

When 1, this bit indicates that the previous reset occurred as a result of a software reset (write to SW RST

bit in the SIM_CONTROL register). This bit will be cleared by any hardware reset or by software. Writing

a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it.

6.5.2.3

COP Reset (COPR)—Bit 4

When 1, the COPR bit indicates the Computer Operating Properly (COP) timer-generated reset has

occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit position will

set the bit, while writing a 1 to the bit will clear it.

6.5.2.4

External Reset (EXTR)—Bit 3

If 1, the EXTR bit indicates an external system reset has occurred. This bit will be cleared by a Power-On

Reset or by software. Writing a 0 to this bit position will set the bit, while writing a 1 to the bit position

Base + $1

Read

SWR

COPR

EXTR

POR

Write

RESET

000

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