7.6 Timing Requirements (continued)

–40°C ≤ TA = TJ ≤ +125°C, 4.5 V < V(IN) = V(P_IN) < 60 V, V( SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT = OPEN,

C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

OVC_tFLT(dly)

FLT assertion delay in over voltage

clamp operation

TPS16632 only

617

µs

SHUTDOWN CONTROL INPUT ( SHDN)

tSD(dly)

SHUTDOWN entry delay

SHDN↓ (below V(SHUTF)) to FET OFF

0.8

1

1.5

µs

CURRENT LIMIT

tFASTTRIP(dly)

Hot-short response time

I(OUT) > I(SCP)

1

µs

Soft short response

I(FASTTRIP) < I(OUT) < I(SCP)

2.2

3.2

4.5

µs

tCL_PLIM(dly)

Maximum duration in current & (power

limiting: TPS16632 Only)

129

162

202

ms

tCL_PLIM_FLT(dly)

FLT delay in current & (power limiting:

TPS16632 Only)

1.09

1.3

1.6

ms

OUTPUT RAMP CONTROL (dVdT)

t(FASTCHARGE)

Output ramp time in fast charging

C(dVdT) = Open, 10% to 90%

V(OUT), C(OUT) = 1 µF; V(IN) = 24V

350

495

700

µs

t(dVdT)

Output ramp time

C(dVdT) = 22 nF, 10% to 90%

V(OUT), V(IN) = 24 V

8.35

ms

POWER GOOD (PGOOD)

tPGOODR

PGOOD delay (deglitch) time

Rising edge

8

11.5

13

ms

tPGOODF

PGOOD delay (deglitch) time

Falling edge

8

10

13

ms

THERMAL PROTECTION

t(TSD_retry)

Retry delay in TSD

MODE = GND

500

648

800

ms

t(Treg_timeout)

Thermal Regulation Timeout

1.1

1.25

1.5

s

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TPS1663

SLVSET9F – SEPTEMBER 2018 – REVISED FEBRUARY 2023

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