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MPC859TZP100A 数据表(PDF) 27 Page - Freescale Semiconductor, Inc

部件名 MPC859TZP100A
功能描述  Hardware Specifications
PDF  96 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MPC859TZP100A 数据表(HTML) 27 Page - Freescale Semiconductor, Inc

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MPC866/MPC859 Hardware Specifications, Rev. 2
Freescale Semiconductor
27
Bus Signal Timing
Figure 10 shows normal case timing for input data. It also applies to normal read accesses under the control of the
UPM in the memory controller.
Figure 10. Input Data Timing in Normal Case
Figure 11 shows the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM
RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
Figure 11. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1
CLKOUT
TA
D[0:31],
DP[0:3]
B16
B17
B19
B18
CLKOUT
TA
D[0:31],
DP[0:3]
B20
B21



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