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MPC8248VRP 数据表(PDF) 21 Page - Freescale Semiconductor, Inc |
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MPC8248VRP 数据表(HTML) 21 Page - Freescale Semiconductor, Inc |
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21 / 60 page ![]() MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 1.5 Freescale Semiconductor 21 AC Electrical Characteristics NOTE Activating data pipelining (setting BRx[DR] in the memory controller) improves the AC timing. Figure 9 shows the interaction of several bus signals. Figure 9. Bus Signals CLKin AACK/TA/TS/ DATA bus normal mode All other input signals PSDVAL/TEA/TA output signals ADD/ADD_atr/BADDR/CI/ DATA bus output signals All other output signals sp11 sp12 sp15 sp10 sp10 sp10 sp30 sp30 sp30 sp30 sp32 sp33 sp35 DBG/BG/BR input signals GBL/WT output signals sp31 input signal ARTRY/TEA input signals sp11a sp10 (except AP) sp10 sp13 DATA bus pipeline mode input signal |
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