MPC8541ECVTAPD datasheet(14/84 Pages) FREESCALE

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MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

RESET Initialization

4.3

Real Time Clock Timing

Table 8 provides the real time clock (RTC) AC timing specifications.

RESET Initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements of

the MPC8541E. Table 9 provides the RESET initialization AC timing specifications.

Table 10 provides the PLL and DLL lock times.

Table 8. RTC AC Timing Specifications

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

RTC clock high time

tRTCH

2 x

tCCB_CLK

——

RTC clock low time

tRTCL

2 x

tCCB_CLK

——

Table 9. RESET Initialization Timing Specifications

Parameter/Condition

Min

Max

Unit

Notes

Required assertion time of HRESET

100

—

μs

Minimum assertion time for SRESET

512

—

SYSCLKs

PLL input setup time with stable SYSCLK before HRESET

negation

100

—

μs

Input setup time for POR configs (other than PLL config) with

respect to negation of HRESET

—

SYSCLKs

Input hold time for POR configs (including PLL config) with

respect to negation of HRESET

—

SYSCLKs

Maximum valid-to-high impedance time for actively driven POR

configs with respect to negation of HRESET

—

SYSCLKs

Notes:

1. SYSCLK is identical to the PCI_CLK signal and is the primary clock input for the MPC8541E. See the MPC8555E

PowerQUICC™ III Integrated Communications Processor Reference Manual for more details.

Table 10. PLL and DLL Lock Times

Parameter/Condition

Min

Max

Unit

Notes

PLL lock times

—

100

μs

DLL lock times

7680

122,880

CCB Clocks

1, 2

Notes:

1. DLL lock times are a function of the ratio between the output clock and the platform (or CCB) clock. A 2:1 ratio results in the

minimum and an 8:1 ratio results in the maximum.

2. The CCB clock is determined by the SYSCLK

× platform PLL ratio.

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