MP7782 – 50W CLASS D MONO BRIDGED AUDIO AMPLIFIER

MP7782 Rev. 1.2

www.MonolithicPower.com

7

8/3/2005

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© 2005 MPS. All Rights Reserved.

TM

Circuit Layout

Proper circuit layout is critical for optimum

performance and low output distortion and

noise. Place the following components as close

to the MP7782 as possible:

1. Power Supply Bypass, C3, C8

C3 and C8 carry the transient current for the

switching power stage. Place a 1µF power

supply bypass capacitor as close to pin 18

(VDD1) and pin 20 (PGND1) as possible. Also

place a 1µF power supply bypass capacitor as

close to pin 13 (VDD2) and pin 15 (PGND2) as

possible.

2. Output Catch Diodes, D3A, D3B, D5A, D5B

D3A, D3B, D5A, and D5B carry the current over

the dead-time while the MOSFET switches are

off. Place D3A between pin 19 (SW1) and pin

20 (PGND1) to prevent the voltage at SW1 from

swinging excessively below ground, and place

D3B between SW2 and pin 18 (VDD1) to

prevent the voltage at SW1 from swinging

similarly to minimize the overshoot and

undershoot of SW2 node.

3. Input Modulator Capacitors, C4

C4 is used to set the amplifier switching

frequency. Place C4 as close to the differential

inputs, pin 2 and pin 3, as possible to reduce

distortion and noise.

4. Electro-Magnetic Interference (EMI)

Due to the switching nature of the Class D

amplifier, care must be taken to minimize the

effects of electromagnetic interference from the

amplifier. However, with proper component

selection and careful attention to circuit layout,

the effects of EMI due to the amplifier switching

can be minimized.

The power inductors are a potential source of

radiated

emissions.

For

the

best

EMI

performance use shielded inductors since the

magnetic field is well contained inside the core.

On the system printed circuit board, trace loops

that carry rapidly changing currents need to be

must be placed as close to the MP7782 as

possible.

Nodes that carry rapidly changing voltage, such

as SW1 and SW2, must be made as small as

possible. If sensitive traces run near SW1 or

SW2, place a ground shield between the traces.

Power Dissipation and Thermal

Considerations

The power dissipation of the MP7782 arises

mostly from the conduction loss of the internal

main switches. This power loss is estimated to

be:

3

.

1

18

.

0

2

R

P

P

L

OUT

LOSS

×

Ω

×

×

≅

Where 1.3 is a temperature coefficient factor

resistance at elevated temperatures.

50W:

W

9

.

3

3

.

1

18

.

0

2

6

50

=

×

Ω

×

×

≅

the resulting temperature rise between junction

and case is approximately 24

°C.

Therefore, caution must be exercised when

using

the

MP7782

in

applications

with

continuous high output power.

A heat sink is required if the MP7782 is applied

at continuous 50W output power.