11-47
RF2514
Rev A5 040115
As an example, consider a loop bandwidth of 300kHz,
a phase margin of 60°, a divide ratio of 64, a KVCO of
33MHz/V, and a KPD of 100μA/2πrad. Time constant
τ1 is 142.15ns, time constant τ2 is 1.98ms, C1 is
0.62pF, C2 is 8.0pF, and R2 is 247.5kΩ.
The control lines provide an interface for connecting
the device to a microcontroller or other signal generat-
ing mechanism. The designer can treat pin 5 (MOD
IN), pin 14 (DIV CTRL), and pin 2 (PD) as control pins
whose voltage level can be set. The lock detect voltage
at pin 13 (LD FLT) is an output that can be monitored
by the microcontroller.
Pin 5 (MOD IN) is the data input to the modulator and
must have a series resistor (RMOD_IN) between it and
the raw data source. The value of RMOD_IN and the
voltage at its input determine the output power level,
with maximum power obtained for RMOD_IN=3kΩ, the
minimum allowable resistance. A three-element filter
structure (series R, shunt C, series R) has been found
to be effective in reducing the out-of-band spectral con-
tent by filtering the higher frequency components of the
baseband data. For this filter, RMOD_IN is the sum of
the two series resistors. The filter values will vary
according to the particular data rate of a given applica-
tion and are best determined experimentally. When the
input to RMOD_IN is a high logic level, the carrier is
transmitted; when the input is a low logic level, the car-
rier is not transmitted. For use as a local oscillator (LO)
source, simply tie the MOD IN pin to the supply voltage
through a suitable series resistor.
Pin 13 (LD FLT) is used to set the threshold of the lock
detect circuit. A shunt capacitor is used to set an RC
time constant with an on-chip series 1k
Ω resistor. The
time constant should be approximately 10 times the
reference period.
General RF bypassing techniques must be observed to
get the best performance. Choose capacitors such that
they are series resonant near the frequency of opera-
tion.
Board layout is always an area in which great care
must be taken. The board material and thickness are
used in calculating the RF line widths. The use of vias
allows IC and component ground pins to be connected
closely to the ground plane, minimizing ground induc-
tance. When laying out the traces around the VCO, it is
desirable to keep the parasitics equal between the two
legs. This will allow equal valued inductors to be used.
It is recommended that pre-compliance testing be per-
formed during the design process to avoid surprises
during final compliance testing, helping to keep the
product development and release on schedule. Pre-
compliance testing can be done with a GTEM cell, an
open area test site, or at a compliance testing labora-
tory.
After the design has been completed and passes com-
pliance testing, then application will need to be made
to obtain final certifications with the respective regula-
tory bodies for the geographic region in which the prod-
uct will be operated.
TROUBLESHOOTING GUIDE
The following measurements were obtained from a
915MHz Evaluation Board.
Test conditions are: VCC=3.00V, RMOD_IN=10kΩ,
VMOD_IN=VCC.
* Dependent on frequency of operation, board layout,
and component variations.
Bibliography
1. Keese, William O., An Analysis and Performance
Evaluation of a Passive Filter Design Technique for
Charge Pump Phase-Locked Loops: Application
Note 1001, National Semiconductor Corp., May
1996.
2. Rhea, Randall W., Oscillator Design and Computer
Simulation, 2nd Ed., Atlanta: Noble Publishing,
1995.
Pin
Number
Pin
Name
Typical DC
Voltage
Ω to GND
(Power Off)
1
GND1
0.00
0
2
PD
3.00
2.7M
3
TX OUT
3.00
1.6M
4
VCC1
3.00
1.6M
5
MOD IN
0.90
1.1M
6
VCC2
2.96
1.6M
7
GND2
0.00
0
8
VREF P
0.91
1.1M
9
GND3
0.00
0
10
RESNTR-
2.63
1.6M
11
RESNTR+
2.63
1.6M
12
LOOP FLT
2.52*
1.9M
13
LD FLT
2.77
234k
14
DIV CTL
3.00
1.6M
15
OSC B
2.83
1.7M
16
OSC E
2.00
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