5

Date: Apr2-07

SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators

© 2007 Sipex Corporation

5

Date: 2//05

SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators

© Copyright 2005 Sipex Corporation

 PIN DFN

PIN CONFIGURATION

PIN NUMBER

NAME

FUNCTION

(fixed)

Regulator Output Voltage. Connect to Pin 

(Adj)

ADJ

Adjustable (Input): Adjustable regulator feed-

back input. Connect to a resistive voltage-

divider network.

2(fixed)

BYP

Reference bypass input for ultra-quiet operation.

Connecting a 0nF cap on this pin reduces

output noise.

2(Adj)

NC

No Connect

3

GND

Ground



EN

Enable/Shutdown (Logic high = enable, logic

low = shutdown)

5

Power Supply Input

6

NC

No Connect

7

NC

No Connect



Regulator Output VoltageA

PiN DESCRiPTiON

PiNOUT 8 PiN DFN

8 PiN OPTiON

SP6203

SP6205

8 Pin DFN

NC

BYP

GND

EN

NC



2

3





7

6

5

FiXED

SP6203

SP6205

8 Pin DFN

VIN

NC

VOUT

GND

EN

NC



2

3





7

6

5

ADJ

NC

ADJUSTABLE