STR91XFA datasheet(13/78 Pages) STMICROELECTRONICS

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STR91xFA

Functional overview

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2.9.3

Interrupt sources

The 32 interrupt request signals coming into the VIC on 32 IRQ channels are from various

sources; 5 from a wake-up unit and the remaining 27 come from internal sources on the

STR91xFA such as on-chip peripherals, see Table 3. Optionally, firmware may force an

interrupt on any IRQ channel.

One of the 5 interrupt requests generated by the wake-up unit (IRQ25 in Table 3) is derived

from the logical OR of all 32 inputs to the wake-up unit. Any of these 32 inputs may be used to

wake up the CPU and cause an interrupt. These 32 inputs consist of 30 external interrupts on

selected and enabled GPIO pins, plus the RTC interrupt, and the USB Resume interrupt.

Each of 4 remaining interrupt requests generated by the wake-up unit (IRQ26 in Table 3) are

derived from groupings of 8 interrupt sources. One group is from GPIO pins P3.2 to P3.7 plus

the RTC interrupt and the USB Resume interrupt; the next group is from pins P5.0 to P5.7; the

next group is from pins P6.0 to P6.7; and last the group is from pins P7.0 to P7.7. This allows

individual pins to be assigned directly to vectored IRQ interrupts or one pin assigned directly to

the non-vectored FIQ interrupt.

Table 3.

VIC IRQ Channels

IRQ Channel

hardware

priority

VIC input

channel

Logic Block

Interrupt Source

0 (high priority)

VIC0.0

WatchDog

Timeout in WDT mode, Terminal Count in Counter Mode

VIC0.1

CPU Firmware

Firmware generated interrupt

VIC0.2

CPU Core

Debug Receive Command

VIC0.3

CPU Core

Debug Transmit Command

VIC0.4

TIM Timer 0

Logic OR of ICI0_0, ICI0_1, OCI0_0, OCI0_1, Timer overflow

VIC0.5

TIM Timer 1

Logic OR of ICI1_0, ICI1_1, OCI1_0, OCI1_1, Timer overflow

VIC0.6

TIM Timer 2

Logic OR of ICI2_0, ICI2_1, OCI2_0, OCI2_1, Timer overflow

VIC0.7

TIM Timer 3

Logic OR of ICI3_0, ICI3_1, OCI3_0, OCI3_1, Timer overflow

VIC0.8

USB

Logic OR of high priority USB interrupts

VIC0.9

USB

Logic OR of low priority USB interrupts

VIC0.10

CCU

Logic OR of all interrupts from Clock Control Unit

VIC0.11

Ethernet MAC

Logic OR of Ethernet MAC interrupts via its own dedicated

DMA channel.

VIC0.12

DMA

Logic OR of interrupts from each of the 8 individual DMA

channels

VIC0.13

CAN

Logic OR of all CAN interface interrupt sources

VIC0.14

IMC

Logic OR of 8 Induction Motor Control Unit interrupts

VIC0.15

ADC

End of AtoD conversion interrupt

VIC1.0

UART0

Logic OR of 5 interrupts from UART channel 0

VIC1.1

UART1

Logic OR of 5 interrupts from UART channel 1

VIC1.2

UART2

Logic OR of 5 interrupts from UART channel 2

VIC1.3

I2C0

Logic OR of transmit, receive, and error interrupts of I2C

channel 0

VIC1.4

I2C1

Logic OR of transmit, receive, and error interrupts of I2C

channel 1

VIC1.5

SSP0

Logic OR of all interrupts from SSP channel 0

VIC1.6

SSP1

Logic OR of all interrupts from SSP channel 1

VIC1.7

BROWNOUT

LVD warning interrupt

VIC1.8

RTC

Logic OR of Alarm, Tamper, or Periodic Timer interrupts

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