LT1016

13

APPLICATIO S I FOR ATIO

1.8

ms, 12-Bit A/D Converter

The LT1016’s high speed is used to implement a very fast

12-bit A/D converter in Figure 15. The circuit is a modified

form of the standard successive approximation approach

and is faster than most commercial SAR 12-bit units. In

this arrangement the 2504 successive approximation reg-

ister (SAR), A1 and C1 test each bit, beginning with the

To get faster conversion time, the clock is controlled by the

window comparator monitoring the DAC input summing

junction. Additionally, the DMOS FET clamps the DAC

output to ground at the beginning of each clock cycle,

shortening DAC settling time. After the fifth bit is con-

verted, the clock runs at maximum speed.

Figure 15. 12-Bit 1.8

ms SAR A-to-D

–

+

LT1021

10V

MSB

LSB

PARALLEL

DIGITAL

DATA

OUTPUT

5V

15V

5V

–5V

5V

–15V

–15V

+

–

GND

COMP

AM6012

AM2504

150k

150k

15k

1k

5V

Q4

Q5

NC

–5V

5V

–15V

5V

2.5k

620

Ω*

620

Ω*

150

Ω

0.01

µF

Q3

Q1 Q2

0V TO 10V

27k

STATUS

9

6

7

5

4

3

1000pF

0.01

µF

SD210

CLK

GND

E

S

CC

D

Q6

1

3

14

11

12

13

14

15

16

17

18

19

20

24

13

10k**

10k

2.5k**

1k

1k

–

+

NC

NC

5V

5V

5V

1k

0.1

µF 10Ω

–5V

–5V

–5V

1k

0.1

µF 10Ω

1/2 74S74

1/2 74S74

1/6 74S04

1/4 74S00

1/4 74S00

1/4 74S08

1/4 74S08

1/6 74S04

PRS

PRS

Q

RST

D

CLK

CLOCK

CONVERT

COMMAND

7.4MHz

IN B

Q

74121

1016 F15

Q1 TO Q5 RCA CA3127 ARRAY

1N4148

HP5082-2810

*1% FILM RESISTOR

**PRECISION 0.01%; VISHAY S-102

–

+

C3

LT1016

C1

LT1016

C2

LT1016

10V